modeling with register

[mohitnegi]

hello ,

 

i wsh to model UART IP so could any one help me in how to model

it with register defined in design spec ....

 

 

Thanks

[apfitch]

What kind of model?

I'd probably just download a VHDL or Verilog model from Opencores...

 

Alan

[mohitnegi]

What kind of model?

I'd probably just download a VHDL or Verilog model from Opencores...

 

Alan

Hi Alan,

 

i wish to do modellng of an IP in systemC and TLM but i am not sure whether  should model

the register map(a dedicated code for all the register used in IP) also ....

IF yes then how would the register map be modelled in systemC and TLM keeping in mind

some of them are read only/ write only , R/w or one shot ....

 

Thanks

Mohit Negi

[apfitch]

Hi Mohit,

  there's no standardisation of that (unlike UVM where there's the Register Layer).

 

For your first question, it depends what the model is for. If you need to share it with software developers, it would make sense to include a memory map and registers, as that is what the software developer expects to see. If the model is completely functional / algorithmic, then you don't need a memory map.

 

Regarding modeling registers, it's the kind of thing that's available in proprietary tools, but I can't think of a non-proprietary modelling solution - perhaps someone else can propose something?

 

In TLM2, all data is transferred as an array of char, so if you want to treat it as accessing particular registers or fields, you'd have to model that yourself. I'll have a quick search on the internet, I'm sure other people must have done things like that,

 

regards

Alan

[apfitch]

This link might be interesting...

http://www.embecosm.com/appnotes/ean1/ean1-tlm2-or1ksim-2.0.html

 

Alan