simulink block to systemC

[srahulkumar1989]

Hi all,

     I am new to the system C and just had learnt about theoretical concepts in systemC. Currently i am trying to translate a simulink model to a systemC model and i have some doubts when i am trying to do.

 

Please refer the below attached simulink model, a counter block is present and the output of the counter block is given as input to the successive block.

 

my doubt is how to send the data from this block to next block . As soon as the count value is increased by 1 it should send the data to the next block and the next block works according to the count value.

 

i tried some code designing the counter block and trying to access in the next block.

 

 

#include "systemc.h"


SC_MODULE (counter1) {


  sc_in<bool>   reset ;      // active high, synchronous Reset input
  sc_in<bool>   enable;      // Active high enable signal for counter
  sc_out<sc_uint<4> > counter_out; // 4 bit vector output of the counter


  //------------Local Variables Here---------------------
  sc_uint<4> count;


  //------------Code Starts Here-------------------------
  // Below function implements actual counter logic
  void incr_count () {
    
    if (reset.read() == 1) {
      count =  0;
      counter_out.write(count);
    // If enable is active, then we increment the counter
    } else if (enable.read() == 1) {
      count = count + 1;
      counter_out.write(count); // writing the current count value at the o/p port.
   
    }
  } // End of function incr_count
  
  SC_CTOR(counter1) {
    cout<<"Executing new"<<endl;
    SC_METHOD(incr_count);
    sensitive << reset;    
  } 


}; 

 

 

Now this count value at the outport is given as the input to the next block.

 

so how do i access this count value in the next block and makes changes according the count value

 

 

Next block code

 

#include "systemc.h"
#include "counter1.h" // including the conter module 


SC_MODULE (Transfer_control) {
sc_in<sc_uint<4> > time_index ;
sc_out<bool> fifo_we ;
sc_out<bool> fifo_re ;


Time_index.read(counter_out.write()) // will this statement read the count value at counter_out port ?
 

but doing this type of code will i have sequential update and access of the count value in the next block?

 

please help me to proceed with it.

 

[ralph.goergen]

Hi. 

 

First of all: you have to be aware of the different execution/simulation semantics of Simulink and SystemC. Simulink is time-triggered Synchronous Data Flow Simulation, SystemC is Discrete Event Simulation. 

If you want to transfer Simulink models to SystemC, you might have a look at SystemC AMS. The TDF (timed data flow) model of computation iss very similar to the simulation semantics of Simulink. 

 

Second: In 

http://www.doulos.com/knowhow/systemc/tutorial/

you can find a small tutorial explaining SystemC and the basics of hierarchical design in SystemC. 

 

Now to your design: 

Assuming that you have connected the the modules correctly (binding the output of M1 to a signal and the signal to the input of M2), you need a process sensitive to the input port. Then this process is activated whenever the value of the input port (and therewith, because of the binding, whenever the signal, means whenever the output port of M1) changes. 

 

But, according to my first comment, be aware of the semantics. Simulink blocks are evaluated in every sample steps. SystemC processes are triggered by events. And a signal in SystemC follows the delta cycle semantics of HDLs. 

 

Greetings

Ralph

[srahulkumar1989]

Hello Mr. Ralph,

                       Thank you very much for your reply, as you said i will have to look upon the timing semantics and its related stuff while transferring a simulink to SystemC model, and will go through heirarchial design too.

 

Regarding the design:

Do i need connect the outport of module M1 to the inport of the model M2 through a signal S and make the process in M2 sensitive to the inport of Module M2. so that whenever the output changes in M1, the input of M2 changes and the process activates. Am i correct? please let me know whether i have the correct understanding of your explanation?

 

Thank you.

[ralph.goergen]

Yes, you are correct. But you need to stimulate/trigger the process in M1 as well to see any changes in the design. 

So far, the method in M1 is sensitive to reset. I.e., it is executed only once, whenever an event occurs at the reset port. 

 

See the mentioned tutorial. It contains three simple modules connected by signals. And it is shown how the connection is set up and how the modules communicate via signals. 

 

Greetings

Ralph