How to model shared memory in SystemC?

[Weiwei Chen]

We need to write functional models with some shared memory features. 

 

Would it be a good idea to have multiple threads in one module sharing its member variable? Or model multiple modules and use port variables for communication?

 

Is there any examples / tutorials online that are worth referring to?

 

Many thanks!! 

[dakupoto]

Please note that threads in any module can always share a member

variable in that module. If you want a full-blown set up, that is threads

in different modules accessing a common resource, why not take a

look at the consumer - producer model, and the built-in classes as

sc_mutex, sc_semaphore ? Hope that helps.

[bennygato]

Please note that threads in any module can always share a member

variable in that module. If you want a full-blown set up, that is threads

in different modules accessing a common resource, why not take a

look at the consumer - producer model, and the built-in classes as

sc_mutex, sc_semaphore ? Hope that helps.

 

I have a similar question... I was asked to "Write five SystemC SC_MODULE master modules that connect to an sc_semaphore." 

but I totally got no idea how to use sc_semaphore to connect modules. do you have any advice?

I read the instruction by accellera but it didn't provide such example.

Thanks!

[dakupoto]

I have a similar question... I was asked to "Write five SystemC SC_MODULE master modules that connect to an sc_semaphore." 

but I totally got no idea how to use sc_semaphore to connect modules. do you have any advice?

I read the instruction by accellera but it didn't provide such example.

Thanks!

Hello Sir,

A few points must be noted.

1. SystemC uses the concept of 'transaction level modelling', which basically

means that processing elelment(PE)s use chennels to exchange data. So any

PE is ONLY concerned with processing data arriving via its input ports, and

sending out the results via an output port. Obviously, all ports have channels

attached to them. Any PE does not care how the channels transfer data

between itself and its neighbor PE.

2. Now coming back to the problem at hand, the sc_semaphore will control

access to a shared resource, but actual data transfer is via some channel.

So, for example, in case of the classic reader - writer problem, the semaphore

will control access to a common data store. In this case, the semaphore will

block the reader from reading data if the data store is empty, and also prevent

the writer from overwriting existing data when the reader is reading that data.

3. When you say you have been told "Write five SystemC SC_MODULE master

modules that connect to an sc_semaphore", one has to ask - where are the

slaves ? If each module is a master, then slaves are missing, and your model

is faulty. There is a very good worked out example in a new SystemC book

that has been published recently, and tackles this shared memory problem

with semaphores.

Hope that helps.