initialization problem with <sc_dt::sc_logic> port

[milind.shende5]

Hello Geniuses, 

 

in my ADC design, I have a output signal "eoc" (end of conversion), I declared it in port declaration like below

 

sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc;

 

In processing function, when I assign it a value '1' like below

 

eoc = '1';

 

I get following error message

 

A2D.cpp: In member function ‘virtual void a2d_nbit::processing()’:

A2D.cpp:50: error: invalid conversion from ‘char’ to ‘sc_dt::sc_logic_value_t’

A2D.cpp:50: error:   initializing argument 1 of ‘sc_dt::sc_logic::sc_logic(sc_dt::sc_logic_value_t)’

 

I also tried to initialize "eoc" in Initialize function like

 

eoc.initialize('1');

 

but then my compiler gives me another error as follows

 

A2D.cpp: In member function ‘virtual void a2d_nbit::initialize()’:

A2D.cpp:28: error: invalid conversion from ‘char’ to ‘sc_dt::sc_logic_value_t’

A2D.cpp:28: error:   initializing argument 1 of ‘sc_dt::sc_logic::sc_logic(sc_dt::sc_logic_value_t)’

 

could you please suggest me how can initialize and assign sc_dt::sc_logic port ?

 

thanks in advance, 

 

Milind.

 

 

 

[Philipp A Hartmann]

The sc_logic constructor taking a char is marked as explicit.  Therefore, you can't pass a char to functions expecting an sc_logic (e.g. initialize).

 

You can either explicitly create (pun intended) an sc_logic from a char, or use the predefined sc_logic constants for assignments and parameter passing:

sc_logic a;
a = sc_logic('1');

eoc.initialize( SC_LOGIC_0 ); // SC_LOGIC_1, SC_LOGIC_X, SC_LOGIC_Z

Greetings from Oldenburg,
  Philipp

[milind.shende5]

Thanks a lot Philipp !!!

your reply really help me and solved the problem. 

 

greetings from Chemnitz.

Milind.

[milind.shende5]

Hello experts, 

I have further problems with my ADC design. 

 

In a A2D TDF module, I have a following ports: 

 

  sca_tdf::sca_in<double> a_in; // analog input pin

 

  sca_tdf::sca_de::sca_in<sc_dt::sc_logic> start;                               //start signal

  sca_tdf::sca_de::sca_in<sc_dt::sc_logic> clk;                                 //clock signal

 

  sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc;                             //end of conversion pin  

  sca_tdf::sca_de::sca_out< sc_dt::sc_lv<8> > d_out;                       // digital output signal

 

I want to trace all the input and output ports in the top_level design. In the top_level design, I have also instantiated a Voltage source, and a internal signal in with type double is declared. 

 

      ________     in              __________________

      | vtg_src |-------------->|  A2D TDF module   |--------> d_out 

      |_______ |      start---->|__________________|--------> eoc

 

I suppose in oder to trace d_out, eoc, and start, I need to connect them to the internal signals. I have tried following approach but the compiler returns with error.

     

//following part is the part of constructor

 

 a2d.a_in(in);

 a2d.d_out(out);

 a2d.start(start);

 a2d.clk(clk);

 a2d.eoc(eoc);

 

 SC_THREAD(start_logic);

 

}

 

private:

 

sca_tdf::sca_signal <double> in;

sc_core::sc_signal<sc_dt::sc_lv<8>> out;

sc_core::sc_signal<sc_dt::sc_logic> start, clk, eoc;

 

could you please suggest me what kind of internal signals I need to use in this case ?

 

thanks in Advance !!!

 

best regards, 

Milind

[Philipp A Hartmann]

Usually it is better to start a new topic in this forum, when there is a new question.

 

Secondly, you should always provide the detailed error message given by the compiler.

 

It is not entirely clear to me, what you are trying to achieve, because you do not show the all relevant parts of the code.  Irrespectively of any tracing, you always need to connect the ports through appropriate channels (TDF or SystemC signals in your case).

 

Last, but not least, a wild guess regarding the compiler error:

 

sc_core::sc_signal<sc_dt::sc_lv<8>> out;

 

In case you've copied the code directly to the browser and depending on your compiler version, you need to insert a space between the two closing template brackets:

sc_core::sc_signal<sc_dt::sc_lv<8> > out;
//              space needed here ^ 

 

Hope that helps,

  Philipp

 

[milind.shende5]

thanks Phillip for the for your suggestion. 

I will open this discussion in a new topic. I will also provide code and compiler errors. 

regards, 

 

Milind.

[DS1701]

On 7/11/2013 at 5:20 AM, Philipp A Hartmann said:

The sc_logic constructor taking a char is marked as explicit.  Therefore, you can't pass a char to functions expecting an sc_logic (e.g. initialize).

 

You can either explicitly create (pun intended) an sc_logic from a char, or use the predefined sc_logic constants for assignments and parameter passing:

sc_logic a;
a = sc_logic('1');

eoc.initialize( SC_LOGIC_0 ); // SC_LOGIC_1, SC_LOGIC_X, SC_LOGIC_Z

Greetings from Oldenburg,
  Philipp

Hi , can you explain the diffrence between " eoc.initialize(false) and  eoc .write ( false) "?

[Philipp A Hartmann]

50 minutes ago, Hook said:

Hi , can you explain the diffrence between " eoc.initialize(false) and  eoc .write ( false) "?

You can call eoc.initialize(...) before the port is bound.

[DS1701]

On 5/22/2018 at 6:13 PM, Philipp A Hartmann said:

You can call eoc.initialize(...) before the port is bound.

Hi @Philipp A Hartmann what is the purpose?

Thanks.

[Philipp A Hartmann]

On 5/24/2018 at 5:36 AM, Hook said:

what is the purpose? 

The purpose of the initialize() function of the signal ports is to set the value of the bound signal at the beginning of the simulation through the given port.