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milind.shende5

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milind.shende5 last won the day on December 11 2013

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About milind.shende5

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  1.    Bicspoili reacted to a post in a topic: Error: CLK failed to set wave to 0 and Sampling id is greater than delay
  2.    Annossyenudge reacted to a post in a topic: initialization problem with <sc_dt::sc_logic> port
  3.    Annossyenudge reacted to a post in a topic: what is the best strategy to model A2D converter ? SC or SC-AMS
  4.    Bicspoili reacted to a post in a topic: initialization problem with <sc_dt::sc_logic> port
  5.    Bicspoili reacted to a post in a topic: what is the best strategy to model A2D converter ? SC or SC-AMS
  6. milind.shende5
    Thanks to Alan and Karandeep for your elaborate replies. Now the things are much clearer to me. so If I have to define a clock, it should be sc_clock clk1(clk1, double_value_period, Time_unit_in_capital, duty_cycle, time_offset, first edge true/false);
  7.    milind.shende5 reacted to a post in a topic: what is default time unit in systemC
  8.    milind.shende5 reacted to a post in a topic: what is default time unit in systemC
  9. milind.shende5
    Thanks for the replies. in SystemC Version 2.0 User's Guide, on page 80, the description about Clock is given. In the example on the same page, the clock is defined as follows sc_clock ck1("ck1", 20, 0.5, 0, true); It states in the description that "This declaration will create a clock object named clock with a period of 20 time units, a duty cycle of 50%, the first edge will occur at 2 time units, and the first value will be true." In the given example, the time resolution is not specified, that means as per the IEEE std 1666-2011, page 102, the default time resolution is 1 ns
  10.    milind.shende5 reacted to a post in a topic: what is default time unit in systemC
  11.    milind.shende5 reacted to a post in a topic: what is default time unit in systemC
  12. milind.shende5
    Hello All, this could be very primitive question, but haunts me from some time. what is default time unit in systemC and how it can be set ? In case of setting clock in the top level module, the clock period can be defined using number of time steps, But I don't know what is the time unit of my module. Where the default time unit can be seen ??? I also want to know this for using advanced simulation controls. thanks in advance, regards, Milind
  13.    milind.shende5 reacted to a post in a topic: what is the best strategy to model A2D converter ? SC or SC-AMS
  14.    milind.shende5 reacted to a post in a topic: Cannot find commonsrcs.h and gendatatrace.h files in systemc-ams package
  15. milind.shende5
    Hello Bogdan, while searching for the missing file in the referenced book, and on this current discussion forum, I got directed to following link by my google browser, which is nothing but a old discussed initiated by the Author of the book himself. http://www.accellera.org/Discussion_Forums/ams_forum/archive/msg?list_name=ams_forum&monthdir=201106&msg=msg00015.html in this link you can see the attachment testcode.tgz. by downloading and uncompressing the attachment, you may get the required files. all the best. regards, Milind.
  16. milind.shende5
    Hello All, Can we use "while loops" in SystemC-AMS constructs (TDF modeling) ? Can somebody refer a tutorial or a reference code which uses while loop in SC-AMS. thanks, Milind.
  17.    milind.shende5 reacted to a post in a topic: what is the best strategy to model A2D converter ? SC or SC-AMS
  18. milind.shende5
    Hello All, I am modeling A2D that uses a successive approximation algorithm. I have modeled A2D converter in SystemC and SystemC-AMS. But both of the models give me some errors. SC model ends up with infinite loop, and SC-AMS model ends with segmentation fault the models are as follows: SC models: Location of the while loop could be the serious problem. I have tried changing the location in side switch statement, but error persists. //error message: stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge st
  19. milind.shende5
    Hello All, I am modeling A2D that uses a successive approximation algorithm. I have modeled A2D converter in SystemC and SystemC-AMS. But both of the models give me some errors. SC model ends up with infinite loop, and SC-AMS model ends with segmentation fault the models are as follows: SC models: Location of the while loop could be the serious problem. I have tried changing the location in side switch statement, but error persists. //error message: stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge st
  20. milind.shende5
    My typo mistake thanks Philip !!!
  21.    milind.shende5 reacted to a post in a topic: can we input a stimuli from a text file ?
  22. milind.shende5
    Hello Torsten, In the above code context, I have written following codes and encountered an error message. could you please help me to locate the mistake? Codes are as follows: -- datalog.txt -- 3.000315 3.000944 3.001572 3.002199 3.002829 3.003457 3.004085 3.004714 3.005342 3.005970 3.006599 3.007227 3.007855 3.008483 3.009112 3.009740 3.010368 3.010997 3.011625 3.012253 3.012881 3.013510 3.014138 3.014766 3.015395 ...cont... -- dummy_source.h -- #include<systemc-ams> #include<systemc> #include<iostream.h> #include<fstream.h> using namespace std;
  23.    milind.shende5 reacted to a post in a topic: can we input a stimuli from a text file ?
  24. milind.shende5
    Hello Torsten, as per the above discussion, I have written the code for a dummy source as follows, I might need ur kind comments. (code runs with out compilation errors) #include<systemc-ams> #include<systemc> #include<iostream.h> #include<fstream.h> using namespace std; SCA_TDF_MODULE (dummy_src) { sca_tdf :: sca_out<double> output; ifstream infile; double val; dummy_src(sc_core::sc_module_name nm, sca_core::sca_time Tm_ = sca_core::sca_time(25, sc_core::SC_US)): output("output"), Tm(Tm_){} void set_attribute() { set_
  25. milind.shende5
    Hello Torsten, thanks for the reply. The time step between the sample is constant. So I will explore the first approach. regards, Milind
  26. milind.shende5
    Hello All, I have a problem regarding Input stimuli. I have a text file, In which I have written an AC signal. Text file example: Time output voltage (volt) 0 us 2.0 v 10 us 2.1 v 20 us 2.2 v . . . 100 us 3.0 v and so on..... I want to use this file, more specifically the "output voltage" signal as an input stimuli to a SystemC-AMS code say for example an amplifier or an A2D converter. in SystemC-AMS code, I do have a signal sca_tdf::sca_signal<double> in; how can i assign the output voltag
  27.    milind.shende5 reacted to a post in a topic: Error: CLK failed to set wave to 0 and Sampling id is greater than delay
  28. milind.shende5
    thanks Torsten for your detailed response. As you correctly pointed out, after removing the two initialize callbacks, the error disappeared. are there some ways to initialize the sca_tdf::sca_de::sca_in<sc_dt::sc_logic> port ? in the simulation, "eoc" and "output" remains "X" undefined. could you please tell me, if the clock connection is correct. I have declared the clock in A2D_toplevel.h, and connected directly to clk input of an a2d instance. In constructor I have defined the clock period as 10, does it take the 10 time units of "set_timestep" attribute a2d_nbit which is
  29. milind.shende5
    Hi All, while simulating A2D convertor, I got following problems. Compilation: No Error running .exe file returns the following error message: ----------------------------------------------------------------------------------------------------------------------------------------------------------------- Warning: SystemC-AMS: Initialization for tracing of: CLK failed set wave to 0 In file: sca_trace_object_data.cpp:136 In process: method_p_0 @ 0 s Error: SystemC-AMS: Sample id (0) is greater than delay (0 while initializing port: A2D_dut.a2d.eoc In file: /home/4all/pac
  30. milind.shende5
    Hello All, thanks for kind replies. The compilation errors are solved !!! The changes made in the code are highlighted in blue color..... #include<systemc-ams.h> #include<systemc> #include<A2D.h> #include<vtg_src.h> using namespace std; using namespace sc_core; SC_MODULE (A2D_top_level) { a2d_nbit a2d; vtg_src input_vtg; sc_core::sc_clock clk1; void start_logic(){ while(true) { start.write(sc_dt::SC_LOGIC_0); wait(2, sc_core::SC_MS); start.write(sc_dt::SC_LOGIC_1); wait(2, sc_core::SC_MS); start.write(sc_dt::SC_LOGIC_0); sc_core
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