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I'm trying to figure out how to get uvm_reg to do register reads over a bus like PCIe, where the read command is decoupled from the read data.  In other words, one transaction on the bus is sending the read command to the DUT (a mem_read TLP, in the PCIe example), and then some indeterminate time later, the response to that read comes as another transaction from the DUT back to the testbench (a completion TLP in PCIe).  uvm_reg seems to assume the simple case where a sequence can call start_item, finish_item, and then the read data has been placed in the original transaction by the driver.  In our agent, the driver is not involved with completions from the DUT at all, the monitor is.

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To krupan,

 

   The register layer is seperated by the uvm_reg_adapter. The transaction layer transmits the information of data, and the signal layer (adapter to the real bus) processes the bus operation.

      I guess the problem of you is sloving the out of order scenario, maybe the first read operation will get feedback after the third read operation feedback, and the register layer can't handle this out of order scenario. So, my suggestion is that don't let the register layer see the scenario, processing the out of order scenario in the signal layer.

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