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Monitor updating before DUT

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I have a DUT that reads and writes to an external memory.  I am simulating this memory device using a SV module in my testbench.  The interface between them is watched by a monitor in a passive agent.  I'm finding that when the DUT writes to the memory, the transactions that are generated by my monitor are correct, but when it reads from the memory, the transactions do not populate correctly.  Stepping through the code in debug mode seems to suggest that the monitor is generating the transaction before the memory module updates the output.  So this seems to be a multiprocessing issue of sorts. Is there something that I can use within UVM that can correct this sequence of events, or is this really a problem within the simulator (Aldec Rivieria)?

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