connecting multiple bus agents to the same 'regmodel'

[iztokj]

Hi,

 

We have an RTL DUT with a large set of registers accessible over I2C, SPI and for fast simulation, it is possible to force the system bus. We would like to be able to have a single instance of the 'regmodel' (a single register mirror) and to use any of the interfaces to manipulate the DUT registers.

 

The UVM standard is supposed to support this requirement by making multiple memory maps containing the same (or not) registers, and each map is then connected to a different bus agent. In practice this works if the default and other maps only contain registers, but it does not work if there are submaps (add_submap). The issue is described here:
http://www.eda.org/svdb/view.php?id=4009

I have looked at the GIT repository, but it seems nobody is trying to fix this:
http://uvm.git.sourceforge.net/git/gitweb.cgi?p=uvm/uvm;a=summary

 

Since it seems this will not be fixed soon while we need it now, what are the proposed alternative solutions?

 

 

I have another somehow related question. We intend to use the regmodel configuration to not only program the DUT, but also to configure a C model (image processing) providing the reference DUT outputs. My first idea was to first manipulate the register mirrors and then to run update twice, once on an actual bus (I2C, SPI) an once on a dummy bus agent accessing a configuration file later parsed by the C reference model. This would not work for two reasons, the issue mentioned above and because memories do not have mirrors. Could anybody suggest me a good UVM approach here. Right now I have the dummy agent accessing an associative array, and we will use it for both the C model and a non UVM bus driver, but this way many advantages of UVM are lost.

 

Regards,

Iztok Jeras