richpodraza Posted March 25, 2013 Report Share Posted March 25, 2013 I hope this description makes sense. In the model I'm working on (which is a port of an existing model in SystemVerilog), there are two threads (rx and tx) that modify some shared flags. I am working on getting my timing as close to the SystemVerilog model as possible, and currently there is a problem of falling behind a few cycles because each cycle, the rx runs after the tx, where in the SV model the tx runs after the rx. I believe that conceptually both threads are supposed to executing concurrently, so I know it may not make good sense to think of one thread executing before the other. So I am wondering what the best way to approach this is. Is there a way to change the order in which threads sensitive to the same clock signal are executed? OR, do I need to concentrate on the shared data and communicate between threads with events? Quote Link to comment Share on other sites More sharing options...
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