forntdoor read failing after backdoor write to a register model while other seq works

[rsbange]

i wrote a UVM sequences for register model with frontdoor/backdoor writes and reads.Everything working well but when any register in the address-map is written via backdoor and then all registers if read from frontdoor attain the same value which was written to that particular register

example-

initially all registers are reset to their default values and read correctly via frontdoor. then register "my_reg" is written a value of "4" via backdoor

reg_model.my_reg.write(status, 4 ,.path(UVM_BACKDOOR),.parent(this)) ;

now if any other register is read via frontdoor using statement -

reg_model.my_reg2.read(status, rd_data ,.path(UVM_FRONTDOOR),.parent(this)) ;

the value returned is "4" which was the value written to "my_reg"

but if the registers are read via backdoor then all value are correctly read.

In other words-

all other scenarios like

frontdoor read after frontdoor write, backdoor read after backdoor write and backdoor read after frontdoor write 'works' but only frontdoor read after backdoor write 'fails'.

Please help and inform where can I be possibly wrong?