scgenmod utility

[chessat2002]

Hi,

I'm currently doing mixed-mode simulations using SystemC testbenches and VHDL/Verilog designs.

For generating SystemC foreign modules, I use the scgenmod utility provided by QuestaSim (V 10.0).

For Verilog designs, I did not face any problems until now.

However, for VHDL designs, scgenmod fails if the top entity contains signed/unsigned data types or generic bitwidths for any data types.

Are there any known work-arounds expect than adapting the entity interface?

Best regards,

Alex'

[apfitch]

If you're lucky someone will know the answer. But you probably first need to read the Questa manuals; and then if that doesn't solve the problem, contact Mentor support,

regards

Alan

[Hans64]

I found this in the just released Questa 10.2 release notes:

dvt29911 - scgenmod would exit with an invalid port type error for VHDL 'signed' datatype. This has been fixed.

Might be it?

Good luck,

Hans.

[Philipp A Hartmann]

For the port widths based on integer generics, you should use the -createtemplate option of scgenmod.

[chessat2002]

Thanks a lot for your fast answers!

@Hans64: thanks for that information, I'll try to switch to version 10.2 ASAP.

@Philipp: this was exactly what I was looking for, I've completly overlooked this option in the manual, thanks a lot.

Alex'