uvm_reg_fifo issues with set_check_on_read()

[JayP]

Hi all,

I'm currently facing a problem with the uvm_reg_fifo class of the uvm register layer when enabling automatic checking on reads. I'm using the uvm_reg_predictor approach with set_auto_predict(0).

In my sequence I'm using the uvm_reg_fifo::set() function within a loop statement in order to initialize the regModel fifo with data items from 0x1, 0x2 ... 0x8. Finally I'm writing all eight data items to the DUT using the uvm_reg_fifo::update() task.

After the update() the mirror of the regModel fifo contains (shows) the last value that I put in using the set() function (0x8). Now the uvm_reg_fifo::get() returns 0x1 as expected. This is the first value written to the fifo and therfore should be the first value which is read. But when using the uvm_reg_fifo::read() and having automatic checking enabled by regModel.set_check_on_read(1) I get the following uvm_error:

UVM_ERROR ../../../../../src/reg/uvm_reg.svh(2893) @ 790: reporter [RegModel] Register "regmodel.FIFO" value read from DUT (0x0000000000000001) does not match mirrored value (0x0000000000000008)

This sequence also fails when simulating the UVM example at .../uvm-1.1b/examples/simple/registers/models/fifo_reg

Why does the uvm_reg_fifo mirror shows and compares against the latest value added ? Shouldn't it compare with the first added value?

Is this as mis-interpretation of the register model from my side?

Any help is really welcome !

Regards,

JayP