StuartSwan
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You might want to try setting a gdb breakpoint on the next() method and then see what code is calling it. That might help you figure out why it is being called twice.. If you are trying to use SCV to do constrained random stimulus, I'd suggest thinking about using SystemVerilog, perhaps also SV UVM. These are much more mature and widely used. There is an example of using an Verilog/SV testbench on a SC DUT in example 45* in the Matchlib examples kit here: https://github.com/Stuart-Swan/Matchlib-Examples-Kit-For-Accellera-Synthesis-WG -Stuart Swan
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If you run this example: https://github.com/Stuart-Swan/Matchlib-Examples-Kit-For-Accellera-Synthesis-WG/tree/master/matchlib_examples/examples/08_dma The log file will have: 8 | id{0x0} addr{0x0} burst{} len{0x0} size{} cache{} auser{} | 6 ns 9 | data{0x1000} last{0x1} wstrb{0x0FF} wuser{} | 6 ns 10 | id{0x0} resp{0x0} buser{} | 7 ns The auser{} has no data inside the curly braces. That means that the bitwidth of that field has been configured to be zero. If you really want the bitwidth of that field to be non-zero, you'll need to create a custom AXI4 configuration class that makes those fields have non-zero widths. There is an example of doing so in this example: https://github.com/Stuart-Swan/Matchlib-Examples-Kit-For-Accellera-Synthesis-WG/blob/master/matchlib_examples/examples/55_mixed_axi/mixed_dma.h
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It is possible that you are not seeing the transaction data in the *data.txt file because you are using an older version of connections.h along with some newer compile options. I recommend upgrading to the latest release here: https://github.com/Stuart-Swan/Matchlib-Examples-Kit-For-Accellera-Synthesis-WG/tree/master Do a clean install, then place your testcase into the kit and try it out and see if that solves the issue. Thanks Stuart Swan
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I recommend searching for and looking at the section titled "Introduction to Channel Logs" in this pdf: https://github.com/Stuart-Swan/Matchlib-Examples-Kit-For-Accellera-Synthesis-WG/blob/master/matchlib_examples/doc/matchlib_training.pdf This will generate a text file of all the transactions in your system. You can use the scripts described to generate a log for just the port/channel of interest. If that isn't quite what you want, you can look at the C++ implementation of the log_hierarchy() method and write your own version that does what you want. The existing logging infrastructure relies on a "callback" mechanism, so you can just implement your own callbacks and plug it into the existing infrastructure. -Stuart Swan
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The Matchlib Connections ResetWrite method models the reset state behavior of a communication channel. This is needed because Matchlib is synthesizable to HW, and sequential HW has reset behaviors. The document describing the method is here: https://github.com/Stuart-Swan/Matchlib-Examples-Kit-For-Accellera-Synthesis-WG/blob/master/matchlib_examples/doc/connections_reference_doc.pdf I recommend looking at the open source kit available via the link below. Within that kit, example 11 shows usage of the ResetWrite method.
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Version 1.0.0
14 downloads
Matchlib Examples Kit for Accellera Synthesis Working Group Stuart Swan Platform Architect Siemens EDA stuart.swan@siemens.com Matchlib is a new open-source SystemC library originally developed by NVidia Research to enable digital hardware to be accurately and efficiently designed and verified at a high level of abstraction, leveraging commercial high level synthesis tools. Some of the key goals of Matchlib are to provide a highly configurable library of HW components that can be directly synthesized to HW with very high quality of results, and to enable very accurate performance simulation of these models in SystemC prior to synthesis, so that the overall design and verification effort is much more efficient. Matchlib contains models for commonly used HW components such as AXI bus fabric components (routers, arbiters, etc), network on chip components, banked memories, crossbars, etc. Matchlib is being actively used by hardware design teams in both industry and academia for advanced hardware design projects, and multiple tapeouts from different groups have occurred for chips that have been almost entirely designed with Matchlib. The recommended location to access the kit is this github link below: https://github.com/Stuart-Swan/Matchlib-Examples-Kit-For-Accellera-Synthesis-WG On-going updates to the kit occur in the above github repository. (Downloads from the Accellera website may not work on certain browsers, and the download from the Accellera website is now out of date.) A video from NVidia Research on Matchlib is here: https://www.youtube.com/watch?v=n8_G-CaSSPU This kit contains a representative set of Matchlib examples and fully self-contained source files and scripts so that the examples can be built and run on any linux compatible system with no other required software. All contents of the kit are open source. Matchlib training slides are available here: https://github.com/Stuart-Swan/Matchlib-Examples-Kit-For-Accellera-Synthesis-WG/blob/master/matchlib_examples/doc/matchlib_training.pdf -
You can use C++ partial template specialization to deduce the template parameters for sc_fixed<> , and then store off the values you find. There is an example of this (to find the dimensions of a C array) in this file: https://github.com/hlslibs/matchlib_toolkit/blob/main/include/auto_gen_fields.h Note the code for finding the size of single dimensional array using partial template specilization: This all should go thru HLS no problem since it all gets resolved in the front end. -Stuart Swan
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Manikanta- The WHVCRouter model in Matchlib is a "wormhole virtual channel" router. It is used in network on chip models. FYI there is a unit test for the router model in the matchlib dir in in the kit at: matchlib-main/cmod/unittests/WHVCRouterTop The model itself is already very close to cycle accurate. Pretty much all of the loops are fully unrolled during HLS, so only the main loop of the main process remains, and that loop may be pipelined during HLS but the pipeline latency is probably just 1. So it is basically very close to RTL, it is just in SystemC . Thanks Stuart Swan
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David Black reacted to a post in a topic:
Large model execution hitting segmentation fault - suggestions?
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Large model execution hitting segmentation fault - suggestions?
StuartSwan replied to Bryan's topic in SystemC Language
Bryan- I don't know what you're modeling but it indeed sounds like a very large system. There are many cases where functionality must be modeled via separate processes (and even dynamic processes). But there are some cases where separate processes are not actually needed. Case in point: you don't necessarily need to use separate processes and sc_fifo to model complex fifo interconnect. It is possible to model the interconnect and fifos all within a single process in many cases, via procedural code. Whether this is applicable in your case depends on what you're trying to achieve in your model. Generally speaking, the more functionality you "collapse" into a single process (rather than using separate processes), the more abstract your model becomes, which is usually a goal with SystemC models. For example, in TLM2 virtual platforms, the general idea is to only have a separate process for each system initiator. -Stuart Swan -
Manikanta- Here are some tips on using Matchlib and the examples: - I recommend using the fully open-source self-contained kit available here: https://forums.accellera.org/files/file/126-matchlib-examples-kit-for-accellera-systemc-evolution-day-2020-presentation/ - Follow the README steps in the top level dir. - You don't need any HLS tools or any other installs to run the examples. - The kit has been successfully downloaded and run on many flavors of Linux machines. - It is easiest probably if you use some version of g++ . - My personal preference if using windows is to use VirtualBox and an Ubuntu Linux virtual machine. If you do this, you can still download Microsoft VSCode from the Ubuntu repositories. - Some people have reported successfully using this kit on cygwin on Windows, though a few minor changes to the Makefiles may be needed for locations of system libs. - Microsoft has something similar to cygwin now in the latest windows (linux shell or something like that), so you can try that too. - The SystemC simulator includes scripts for building with Visual Studio, but the other code in the kit I don't think has been tested with Visual Studio. Thanks Stuart Swan
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Diamantis- I suggest that you download the Matchlib examples kit on the Accellera website: https://forums.accellera.org/files/category/2-systemc/ Then I recommend reading the PDF at matchlib_examples/doc/catapult_user_view_scheduling_rules.pdf In particular note the section on "Avoiding Pre-HLS and Post-HLS Simulation Mismatches". Note the recommendation to if possible avoid use of non-blocking message passing IO. I think you should try to replace your stall signal that uses PopNB with a regular systemc signal. I would imagine that the stall condition is "transient", ie. the writer might assert stall, but if the reader never reads it until later, the stall condition might disappear. Signals are good for modeling this, message passing interfaces are not, since messages are always reliably delivered between producer and consumer. You probably should also explicitly test the stall condition in your pre-HLS SystemC model, even if that means forcing the condition to occur. Here are some papers on using HLS for RISCV processors that may be helpful: http://www.cs.columbia.edu/~luca/research/mantovani_CICC20.pdf https://webthesis.biblio.polito.it/6438/1/tesi.pdf Thanks Stuart Swan
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Version 5.0.0
110 downloads
Matchlib: A New Open-source Library to Enable Efficient Use of High Level Synthesis Stuart Swan Platform Architect Mentor, A Siemens Business stuart_swan@mentor.com Note: This download is now obsolete. The updated download can be accessed here: https://forums.accellera.org/files/file/127-matchlib-examples-kit-for-accellera-synthesis-working-group/ Matchlib is a new open-source SystemC library developed by NVidia Research to enable digital hardware to be accurately and efficiently designed and verified at a high level of abstraction, leveraging commercial high level synthesis tools. Some of the key goals of Matchlib are to provide a highly configurable library of HW components that can be directly synthesized to HW with very high quality of results, and to enable very accurate performance simulation of these models in SystemC prior to synthesis, so that the overall design and verification effort is much more efficient. Matchlib contains models for commonly-used HW components such as AXI bus fabric components (routers, arbiters, etc), network on chip components, banked memories, crossbars, etc. Matchlib is being actively used by hardware design teams in both industry and academia for advanced hardware design projects, and multiple tapeouts from different groups have occured for chips that have been almost entirely designed with Matchlib. A video from NVidia Research on Matchlib is here: https://www.youtube.com/watch?v=n8_G-CaSSPU This kit contains a representative set of Matchlib examples presented at Accellera SystemC Evolution Day 2020 and fully self-contained source files and scripts so that the examples can be built and run on any linux compatible system with no other required software. All contents of the kit are open source. -
Version 1.1
232 downloads
STMicroelectronics, ARM and Cadence Improve Tool and Model Interoperability with Three Joint Contributions to Accellera Systems Initiative Proposed Interfaces for Interrupt Modeling, Register Introspection and Modeling of Memory Maps Enable Third-Party Model and Tools Markets Geneva, Switzerland, Cambridge, UK, San Jose, California, July 29, 2013 -- STMicroelectronics, ARM and Cadence Design Systems, Inc. today announced three new contributions to the SystemC Language Working Group of the Accellera Systems Initiative. This collaboration will further increase model and tool interoperability for electronic system-level (ESL) design at the transaction-level. The joint work includes new interfaces for interrupt modeling, which allow seamless integration of models from different companies; application programming interfaces for register introspection that enable tool interoperability to seamlessly display and update register values; and new approaches for memory-map modeling that improve users’ productivity during debugging of virtual platforms for hardware/software multicore systems. The contributions consist of fully working application programming interfaces (API) and implementations, as well as documentation and examples, released under an Apache 2.0 open-source license and available online at http://forums.accellera.org/files/. “These new interfaces are crucial to strengthening the ESL ecosystem. As a step towards interoperability driven by ST, ARM and Cadence, these proposed standards dramatically reduce risks and efforts associated with the integration of virtual prototypes. Eliminating the need for adapters will increase virtual prototype simulation performances, enable sooner and faster hardware-software integration, and therefore improve product time-to-market,” said Philippe Magarshack, executive vice president, Design Enablement & Services, STMicroelectronics. “Cadence has worked closely with ST, ARM and other partners to develop these open standards proposals,” said Stan Krolikoski, distinguished engineer, Cadence. “Adoption of these proposed standard interfaces in virtual prototyping solutions will enable the expansion of the ESL ecosystem and provide added value through interoperability to users.” “The Accellera TLM 2 standard has been very important in enabling an ecosystem of models that can be integrated into SystemC virtual prototypes,” said John Goodenough, vice president of Design Technology and Automation, ARM. “By addressing a key gap in the model-to-model interface and by enhancing tool integration, these proposed contributions further help in ensuring virtual prototypes can be predictably and consistently integrated.” "With the growing adoption of virtual prototypes for early software development, it is important to continue to simplify their creation while adding value for users,” said Yatin Trivedi, director, standards and interoperability at Synopsys. “As a market leader in virtual prototyping, we welcome contributions and discussions that help to advance the Accellera SystemC TLM standard." “We look forward to working together and collaborating in the Accellera Systems Initiative SystemC Language Working Group to advance the needs for improved virtual prototyping model and tool interoperability,” said Shabtay Matalon, ESL market development manager from Mentor Graphics Corporation. “The initial open source contributions serve as a good catalyst to start the process of addressing and refining these pressing standards challenges.” The first technical proposal addresses the need for better interoperability among SystemC TLM (Transaction Level Modeling) models and proposes a standard interface to model interrupts and wires at the Transaction Level. This will enable seamless integration of models from different companies with standardized memory-mapped connections, further enhancing the growth of a market for third-party TLM models. The second proposal defines a standard interface between models and tools to support register introspection, enabling tools to seamlessly display and update register values. This interface works in a mix of different user-defined register classes to support platforms integrating heterogeneous models from various model providers. This capability is a key enabler for integration and debug of embedded software on pre-silicon virtual prototypes. The third proposal introduces an approach to reconstruct system memory maps as seen from initiators, enabling ESL tools to support hardware/software debug on complex virtual platforms, for which understanding of the memory maps is instrumental. It addresses the challenge that memory maps depend on the interconnection of models and as a result each system initiator might have its own view. With these new contributions, ST, ARM and Cadence expect the integration of SystemC models in virtual prototypes will be significantly improved for all users, enabling the models’ quick and efficient deployment. In addition, standard interfaces between models and tools will extend hardware/software integration and debug capabilities using appropriate tools. Within the Accellera Systems Initiative, ARM, Cadence, and ST plan to work with other companies to refine and fully standardize these proposals. -
StuartSwan joined the community
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666 downloads
This contribution contains a small, working example that demonstrates a general purpose, scalable approach for integrating UVM-SV and UVM-e models with SystemC TLM2 models. Please see the PACKAGE_README.txt file and the uvm_tlm2_integration.pdf slides within thekit for further information on this example. Full source code and run scripts are provided within the kit.
