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Thank you uwes! But I still got problems. 1. You said "you use the new phasing (_phase) BUT then you should object the end of the phase and not uvm_test_done" I think your meaning is use this code class test extends uvm_test; ... task main_phase(uvm_phase phase); phase.raise_objection(this); phase.drop_objection(this); endtask endclass Do not use this one in pre_body: uvm_test_done.raise_objection(); in post_body: uvm_test_done.drop_objection(); Is that correct? Or, would you please give me some code examples? 2. I just want to know how driver and sequence interoperate <1> once the driver call get_next_item, the body() in sequence will be called <2> body() can only be called one time. It generate many items and put them is a 'fifo'. get_next_item get item from fifo Which one is correct? My experiment seems to show that <2> is correct. Do you agree with it? Thank!

I use these functions like this In uvm_test virtual task run_phase(uvm_phase phase); super.run_phase(phase); phase.raise_objection(this); `uvm_info(get_type_name(),"I'm in dprx_test run before delay", UVM_LOW) #1000000 print_config(); `uvm_info(get_type_name(),"I'm in dprx_test run after delay", UVM_LOW) phase.drop_objection(this); endtask:run_phase In uvm_sequence: virtual task pre_body(); // p_sequencer.get(x_aux_inst); if (starting_phase != null) starting_phase.raise_objection(this,"user_seq not finished"); `uvm_info(get_type_name(),"I'm in seq pre_body", UVM_LOW) endtask: pre_body virtual task body(); uvm_test_done.raise_objection(this); x_aux_inst = new("x_aux_inst"); x_aux_inst.data_len = 1; x_aux_inst.command = 4'b10_00; `uvm_do(x_aux_inst) uvm_test_done.drop_objection(this); `uvm_info(get_type_name(),"I'm in seq body", UVM_LOW) endtask virtual task post_body(); if (starting_phase != null) starting_phase.drop_objection(this,"user_seq finished"); endtask Is there any problems here?

Hi, I am a UVM initiator and I set up a test bench using UVM. In this test bench there is one sequence and one sequencer called "aux_inst_seq" and "aux_inst_sqr" I register the aux_inst_seq with uvm_sequence_utils. I register aux_inst_sqr with uvm_sequencer_utils. I also set aux_inst_seq as default sequence in uvm_test at building phase with uvm_config_db. In order to test that aux_inst_seq is called, I add uvm_info to pre_body and post_body of aux_inst_seq Now these log has not been printed out which shows that the sequence function fails BTW, 1. I checked the connect in agent and I think it is all right? 2. Does this problem has something to do with raise/drop_objection? 3. How to know uvm_config_db is all right? 4. I'm using UVM_1.1 version How can I debug this problem? Thank you!