tyee

Members

tyee's Achievements

UVM-ML Open Architecture

tyee commented on oritk's file in UVM

Hi, I want to know if it is possible to compile and run pure SystemC code using the UVM-SystemC framework (without vcs) from UVM-ML.
- September 19
- 17 comments
- - uvm-ml
  - verification
  - (and 2 more)
    Tagged with:
    
    uvm-ml
    
    verification
    
    uvm
    
    multi-language
tyee started following Is it possible to integrate UVM-SystemC and UVM-ML in the same testbench environment? September 18
Is it possible to integrate UVM-SystemC and UVM-ML in the same testbench environment?

tyee posted a topic in SystemC Verification (UVM-SystemC, SCV, CRAVE, FC4SC)

Hello, I'm trying to use UVM-SystemC and UVM-ML within the same environment. My goal is to run a UVM-SystemC testbench to simulate the C model (without using VCS) and use UVM-ML for running RTL (which requires VCS). However, the UVM-SystemC component in UVM-ML seems to be a 'minimalistic' version of UVM-SystemC, and there are some differences between the two. For example, UVM-ML's UVM-SystemC employs a barrier mechanism for phases, while UVM-SystemC uses an objection mechanism. Is it possible to combine UVM-SystemC and UVM-ML in the same testbench environment?
- September 18
- - uvm-systemc
  - uvm-ml