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Showing results for tags 'uvm-systemc'.
Hi, I started to play around with the basic scoreboard example provided in the uvm-systemC 1.0 beta 2 release. I was trying to enhance the example by adding a clock and a reset signal in the sc_main. Then I wanted to modify the vip_if to add a reset and clock signal. My goal was to implement a driver/monitor run phase that drives/samples the sig_data signal on the rising edge of the clock. I am struggling to do so... Is there such an example that exists or that someone could share ?
Hi, following code that comes with the crave example does not override the sequence item type used by the test: jelly_bean_transaction::type_id::set_type_override(sugar_free_jelly_bean_transaction::get_type()); neither does: uvm_set_type_override(jelly_bean_transaction::get_type(), sugar_free_jelly_bean_transaction::get_type()); Which in my opinion should work as it is a type override on a uvm_object type and furthermore is a derived class of jelly_bean_transaction that only adds a constraint to the class. Any clue why this does not work but overriding a type deri