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fayz
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fayz reacted to a post in a topic: Top module related error help required.
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I have commented some ports in both SOC and rv-thunder module due to which i think error occurs, plus i had verified the rv-thunder module through testbench,which is working fine, here is updated version of code: https://www.edaplayground.com/x/QQcs Moreover, do you know any way to name these ports, so that it would be easy for debugging i.e Error: (E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'TOP.thunder_inst.port_4' (sc_out)
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hey @AmeyaVS, If commented line 83,84 and 23,24 i.e input ports of rv-thunder module and their respective port binding in SOC module line 23 and 24 , now i get error related to output port: Error: (E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'TOP.thunder_inst.port_4' (sc_out) In file: D:\Download Data\new download\systemc-2.3.4\systemc-2.3.4\src\sysc\communication\sc_port.cpp:235
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The problem occurs when connecting the ports in SOC module(TOP module), am i making a mistake?: Error: (E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'TOP.thunder_inst.port_6' (sc_in) In file: D:\Download Data\new download\systemc-2.3.4\systemc-2.3.4\src\sysc\communication\sc_port.cpp:235 here is the link of the code: https://www.edaplayground.com/x/JfnT I want to achieve something like this shown in below picture.
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Is it possible to perform operations on sc_signal in top module then connecting to ports?
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#include <systemc.h> #include "fetchunit.h" SC_MODULE(DECODE_R) { sc_out<sc_int<7>> opcode; sc_out<sc_int<5>> rd,rs1,rs2; sc_out<sc_int<3>> func3; sc_out<sc_int<7>> func7; sc_in < sc_int<32>> writedata; sc_in_clk clk; SC_CTOR(DECODE_R) { SC_THREAD(rtype); sensitive << clk.pos() ; } void rtype() { while (true) { wait(clk.posedge_event()); cout << writedata.read().range(6, 0).to_int() << endl; if (writedata.read().range(6, 0) == 51 && writedata.read().range(14, 12) == 0 && writedata.read().range(31, 25) == 0) { cout << "R-TYPE ADD INSTRUCTION" << endl; opcode.write(writedata.read().range(6, 0)); rd.write(writedata.read().range(11, 7)); func3.write(writedata.read().range(14, 12)); rs1.write(writedata.read().range(19, 15)); rs2.write(writedata.read().range(24, 20)); func7.write(writedata.read().range(31, 25)); } else { cout << "code running" << endl; } } } }; SC_MODULE(TopLevelModule) { FETCH fetch_inst; DECODE_R decode_r_inst; sc_signal<sc_int<32>> writedata_signal; sc_signal<sc_int<5>> rd, rs1, rs2; sc_signal<sc_int<3>> func3; sc_signal<sc_int<7>> func7, opcode; sc_signal<bool> clk; SC_CTOR(TopLevelModule) : fetch_inst("FetchInstance"), decode_r_inst("DecodeRinstance") { fetch_inst.writedata(writedata_signal); fetch_inst.clk(clk); decode_r_inst.opcode(opcode); decode_r_inst.rd(rd); decode_r_inst.rs1(rs1); decode_r_inst.rs2(rs2); decode_r_inst.func3(func3); decode_r_inst.func7(func7); decode_r_inst.writedata(writedata_signal); decode_r_inst.clk(clk); } }; int sc_main(int argc, char* argv[]) { sc_set_time_resolution(1, SC_SEC); sc_clock clk("clk", 2, SC_SEC); sc_signal<sc_int<32>> writedata_signal; TopLevelModule TOPMODULE("TOP"); sc_trace_file* tf = sc_create_vcd_trace_file("decode"); sc_trace(tf, TOPMODULE.decode_r_inst.clk, "clk"); sc_trace(tf, TOPMODULE.decode_r_inst.writedata, "writedata"); sc_trace(tf, TOPMODULE.decode_r_inst.opcode, "opcode"); sc_trace(tf, TOPMODULE.decode_r_inst.rd, "rd"); sc_trace(tf, TOPMODULE.decode_r_inst.rs1, "rs1"); sc_trace(tf, TOPMODULE.decode_r_inst.rs2, "rs2"); sc_trace(tf, TOPMODULE.decode_r_inst.func3, "func3"); sc_trace(tf, TOPMODULE.decode_r_inst.func7, "func7"); sc_trace(tf, TOPMODULE.fetch_inst.pc_value, "pc"); sc_start(5, SC_SEC); sc_close_vcd_trace_file(tf); return 0; }
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#include <systemc.h> SC_MODULE(FETCH) { sc_out<sc_int<32>> writedata; sc_in < sc_int<32>>readdata32_16; sc_in_clk clk; sc_int<32>* mem; sc_uint<12> pc_value = 0; sc_int<32>* ptr; int i = 0; sc_in<bool> res; SC_CTOR(FETCH) { int memsize = 4096; mem = new sc_int<32>[memsize]; /** for (int i = 0; i < memsize; i++) { mem[i] = 0; }*/ SC_THREAD(memoryAccessThread); sensitive << clk.pos(); SC_THREAD(checkins); sensitive << clk.pos() ; SC_THREAD(reset); sensitive << clk.pos(); } void memoryAccessThread() { while (true) { wait(); if (i >= 0 && i < 4096 && res!=1) { // for Checking bounds of memory before writing mem[i] = readdata32_16; } } } void checkins() { while (true) { wait(clk.posedge_event()); if (i >= 0 && i < 4096 && res!=1) { if (readdata32_16.read().range(31,16)==0){ //for 16 bit instruction writedata.write(mem[i]); pc_value = pc_value + 2; ptr = &mem[i]; i++; cout << "16 bit running" << endl; } else if (readdata32_16.read() != 0 && res != 1) { //for 32 bit instruction writedata = mem[i]; pc_value = pc_value + 4; ptr = &mem[i]; i++; cout << "32 bit running" << endl; } } } } void reset() { while (true) { wait(clk.posedge_event()); if (res == true) { ptr = &mem[0]; i = 0; pc_value = 0; readdata32_16 =0 ; writedata = 0; } } } ~FETCH() { delete[] mem; } }; int sc_main(int argc, char* argv[]) { sc_set_time_resolution(1, SC_SEC); sc_signal<sc_int<32>> write, read; sc_signal<bool> reset; sc_signal<sc_uint<12>> pcvalue; sc_clock clk("clk", 2, SC_SEC); FETCH fetch_module("fetch_module"); fetch_module.writedata(write); fetch_module.readdata32_16(read); fetch_module.clk(clk); fetch_module.res(reset); sc_trace_file* trace_file = sc_create_vcd_trace_file("fetch"); sc_trace(trace_file, write, "write"); sc_trace(trace_file, clk, "clk"); sc_trace(trace_file, read, "read"); sc_trace(trace_file, reset, "reset"); read = 0x289f45e1; sc_start(2, SC_SEC); cout << "ptr :" << fetch_module.ptr << endl; read = 0x6e3f1290; sc_start(2, SC_SEC); cout << "ptr :" << fetch_module.ptr << endl; read = 0x0000ffff; sc_start(2, SC_SEC); cout << "ptr :" << fetch_module.ptr << endl; reset = true; sc_start(2, SC_SEC); cout << "ptr :" << fetch_module.ptr << endl; /* read = 0x00e2ffff; sc_start(2, SC_SEC); cout << "ptr :" << fetch_module.ptr << endl;*/ sc_close_vcd_trace_file(trace_file); cout << "pc value :" << fetch_module.pc_value << endl; for (int i = 0; i <= 4095; i++) { cout << "memory " << i << ": " << hex << fetch_module.mem[i] << dec << endl; } return 0; }
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fayz joined the community
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I am having difficulties in setting up systemC through visual studio code on ubuntu, when i run a code i got path error. #include errors detected. Please update your includePath. Squiggles are disabled for this translation unit (/home/fayz/systemC/full adder.cpp). cannot open source file "systemc.h"