I am trying to use +uvm_set_default_sequence to set default sequence to an parameterized sequence, but i didn't make it. Can anyone please help and show me what went wrong?
The sequence is parameterized like below.
class seq_a #(int param = 10) extends uvm_sequence;
//`uvm_object_utils(seq_a)
`uvm_object_param_utils(seq_a#(param))
function new(string name = "my_seq");
super.new(name);
do_not_randomize = 1'b1; // Required for ModelSim
set_automatic_phase_objection(1);
endfunction
task body;
uvm_sequence_state_enum state = get_sequence_state();
// In UVM 1.1d: starting_phase.raise_objection(this);
`uvm_info("SEQ_A", $sformatf("state is %s",
state.name()), UVM_LOW);
while ($time < 10us) begin
#1us;
`uvm_info("SEQ_A", $sformatf("[%d] ping at time %d", param, $time), UVM_LOW);
end
// In UVM 1.1d: starting_phase.drop_objection(this);
endtask
endclass
And I added +uvm_set_default_sequence=*,main_phase,seq_a#(10) to VCS runtime option.
Unfortunately, it went wrong, and log was like below.
UVM_INFO @ 0: reporter [RNTST] Running test test...
UVM_WARNING @ 0: reporter [UnknownTypeName] find_wrapper_by_name: Type name 'seq_a#(10)' not registered with the factory.
UVM_ERROR @ 0: reporter [UVM_CMDLINE_PROC] Invalid type 'seq_a#(10)' provided to +uvm_set_default_sequence
UVM_FATAL @ 0: reporter [BUILDERR] stopping due to build errors
