Hello ,
Iam trying to verify the router design ...but getting error as follows.
** Error: (vsim-7065) Illegal assignment to class work.router_pkg::router_wr_seqr from class mtiUvm.uvm_pkg::uvm_sequencer #(class work.router_pkg::write_xtn, class work.router_pkg::write_xtn)
# Time: 0 ns Iteration: 0 Region: /router_pkg File: ../tb/router_tb.sv Line: 37
begin
foreach(v_seqrh.wr_seqr[i])
v_seqrh.wr_seqr[i]=wr_agt_t.wr_agt[i].wr_seqr; //error line//
foreach(v_seqrh.rd_seqr[i])
v_seqrh.rd_seqr[i]=rd_agt_t.rd_agt[i].rd_seqrh;
end
