ManikantaAllam

"concat_sim_rtl.v", 4519: sc_main.my_testbench.router.ccs_rtl.dut_inst.router.WHVCSourceRouter_1_4_2_8_WHVCRouterTop_Flit_t_16_process_inst.WHVCRouterBase_1_4_2_8_WHVCRouterTop_Flit_t_receive_credit_for_6_WHVCSourceRouter_1_4_2_8_WHVCRouterTop_Flit_t_16_process_WHVCRouter_h_ln113_assert_credit_recvOS_i_CS_le_buffersize_and_TotalcreditsreceivedcannotbelargerthanBuffersize: started at 4895000ps failed at 4895000ps # Offending 'pcredit_recv_i_buffersize_Total_credits_received_cannot_be_larger_than_Buffer_size_prb_5' Hi @Matt Bone, I tried the latest repo you provided. Unfortunately, it also has the same faults. Above is the warning from the RTL simulation. Perhaps you should have run the WHVCRouter example with 1 virtual channel configuration. To run the same example that I run, 1. Go to 'WHVCRouterTop.h' in /matchlib-main/cmod/unittests/WHVCRouterTop/ and edit line 31 with 2 VCs (kNumVChannels = 2), and line 45 flit field with packetID 2bits ( typedef Flit<64, 0, 0, 2, FlitId2bit, WormHole> Flit_t;) 2. Go to 'testbench.cpp' in /matchlib-main/cmod/unittests/WHVCRouterTop/ and uncomment the line 347 (flit.packet_id = vc;) 3. go to 'run_hls_global_setup.tcl' in /matchlib-main/hls/ and edit line 43 to make sysC version 2.3.3 (solution options set /Flows/VCS/SYSC_VERSION 2.3.3) 4. go to 'hls_Makefile' in /matchlib-main/hls/ and edit clock period to 5ns (export CLK_PERIOD ?= 5) (design failed to schedule at default clk period) 5. Make sure all the env variables are set properly VCS, Verdi, Catapult and ...etc., 6. Go to /matchlib-main/hls/unittests/WHVCRouterTop/ start make This will run the example and show the faults I am encountering. Thank you & best regards Manikanta

Hi @Matt Bone & @StuartSwan, I am trying to run the matchlib HLS flow for WHVCRouter with 2 virtual channel configuration (cmod & hls unittests from the kit). No other changes at all. The design at RTL simulations shows some credit overflow warnings, but shows the simulation is passed. OSCI simulation has no issue at all. Unfortunately, the send and receive count of the traffic in testbench are being affected due to this. I am unsure whether to consider this as a bug or some other kind of issue, or no issue at all. What would be your comment on it? Thanks in advanvce & best regards Manikanta

Hi @Matt Bone, These are some nontrivial insights into the knowledge required. Thank you so much. Best regards Manikanta

Hi @StuartSwan, A general question on the flow, how the debugging is done at RTL+untimed_C++ level? There's no apparent bug in systemC simulations but at RTL it shows design error. How to debug this sort of bugs in the design? Best regards Manikanta

Hi @StuartSwan, I am trying to do hls flow using the kit you provided. Unfortunately, I am only able to use latest gcc version later than 10.0. There are some issues with the hls, especially with RTL simulations using VCS. Could you point out something useful or I am missing? I will provide the log. Thanks & regards manikanta PS: Solved by correctly pointing VCS/GNU package. And changing the right systemC version in 'run_hls_global_setup.tcl'.

Hi seniors. My question is regarding a C++ concept. Not directly SystemC. I am dealing with a set of SystemC Template classes (Nvidia's MatchLib Library). The classes here use template-based parameter initialization instead of a constructor. I am writing a simulation framework using the elements from this library. I need to do a lot of looping through some parsing structures during instantiations and port mappings - runtime deduction of values. I have concerns about moving those parameters from the templates to the constructors - I am not thinking of this as a solution. So, is there any solution to these kinds of situations? Thank you so much in advance! PS: I'm not thinking of printing the code either now!

@StuartSwan Hi Swan, Thank you so much for replying. Yes, I am creating a heterogeneous NoC simulation framework as part of my thesis. I will also modify this router to have different number of virtual channel distribution per ingressport unlike the original one has uniform distribution of no. of virtual channels on all the input ports. I have seen and simulated unittests _ WHVC router example already. But also saw all the processes(functions involved in routing) are put in single clocked process. That's where I had the concern regarding the latency mismatch between after HLS and pre HLS simulations. Nevertheless, this level of detailing is sufficient for system level exploration I guess. I will further see and try to understand it. Thank you again. Best regards Manikanta

@StuartSwan Hi Swan, I am interested in WHVCSource Router, as part of creating a cycle accurate simulation frame work. The router itself is kind of loosely/un-timed implementation as the unrolling and pipelining are left to HLS Tool. Is there a way, which I am missing and must know, that enables system level cycle accurate(approx.) fast simulation without depending on the RTL? Somewhere, in one of Siemens' webinars, I heard about Back Annotation. Unfortunately, I could not understand it as I am a beginner and could not find any example. Is there something you could comment on this? TIA & Best regards Manikanta

@StuartSwan Thank you so much for the quickest reply. I'll try it out.

Hello seniors, I am trying to use NVIDIA'S matchlib's components (cmod & LI Channels) for the first time. I'm wondering if I can instantiate & run these directly with systemc & C++ ( Visual Studio - Windows OS) as same as other systemc modules? If I can avoid HLS tools' intervention, how can I do this? I am not interested in the synthesis for now. The reason I am interested in this library is its generic nature and HLS-ability. For now, I am just interested in writing a simulation framework and using it as part of my other work. @StuartSwan I hope you could give me some hints regarding this. Thank you & Best regards Manikanta

Thank you so much Mr. David. Most of the literature regarding SoC communication modelling ( Buses/NoCs) termed as 'cycle accurate TLM simulations'. So I just wanted to get the clarity over this. Best Regards Manikanta

Dear Seniors, I am new to SystemC. I come from VHDL Background. As part of my master's thesis, I am going to use the Cycle Accurate TLM modelling methodology. Though I have gone through various examples I am quite not able to get the sense of Cycle Accurate TLM models. Could anyone lead me to a library of examples (Could be a textbook/git library/ anything) that can be simulated and understood for the above-mentioned use case? or even briefly explain with a simple baseline example? Thank you & Best regards Manikanta