SeanChou Posted November 30, 2012 Report Share Posted November 30, 2012 (edited) Hi UVM connect export, I hope to use tlm_analysis_port in direction SV report to SC (I could only find the other direction in uvmc example) so I try to write my own as following. By printing some message I found the analysis port in SV side has been written, however the SC side write did not be invoked, could some one give some hint to the problem or how to debug it has been connected correctly? (I am new to SC so there could be some stupid mistake, please forgive me if any) thanks! SC: class my_subscriber : public sc_module, public tlm_analysis_if <my_pkt> { virtual void write (const my_pkt &pt) { //... } } int sc_main (int argc, char** argv[]) { my_subscriber sub("sub"); // uvm_connect(sub, "my_ap"); // I modified previous line to following 2 lines // because ambiguous call due to multiple inheritance uvmc_analysis_port<my_pkt> port (sub.name(), "my_ap"); port.bind(cons); sc_start(); return 0; } SV: uvmc_tlm1 #(my_pkt)::connect(uvm_ap, "my_ap"); Edited November 30, 2012 by SeanChou Quote Link to comment Share on other sites More sharing options...
mpeer Posted November 30, 2012 Report Share Posted November 30, 2012 Hi SeanChou, If you are using vcs tool, there are some examples in <INSTALL_PATH>/doc/examples/systemc/vcs/SV_SC_analysis and <INSTALL_PATH>/doc/examples/systemc/vcs/SC_SV_analysis These examples might be useful for you. Regards Peer Mohammed Quote Link to comment Share on other sites More sharing options...
Recommended Posts
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.