loglong

OK, I got it. Yes, you're right, I have missing import the vip block. This problem is fixed after state the import. Thanks again.

Thanks, uwes. I have no protected or private variable since it just a test testbench. I have deleted virtual sequencer, to make the compile pass first, maybe I can try it in VCS as well later.

Hi, I have derive the virtual sequencer class from the uvm_sequencer class class uart_tb_vsd extends uvm_sequencer; but it reported syntax error as: *E,SVNOTY (/home/gendaili/projects/uvm_tb/verif/sv/uart_tb_vsd.sv,4|38): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope. ------ In SystemVerilog syntax, if a datatype begins with an identifier, the identifier must refer to a type. Make sure that the typedef of the desired type is visible in that scope or that there are not multiple wild card import clauses importing typedefs of the same identifier name. The latter would make the use of a simple type name ambiguous; in that case, in order to disambiguate which type is desired you must provide a full type name of the form package_name::type_name. What's wrong with it? is it require a specific sequence item like: class uart_tb_vsd extends uvm_sequencer #(uart_transfer) ; Please help me out, thanks.

We're starting a new projects, and arguing with the VMM and UVM. there're few vip are written by VMM, but we want to migrate to UVM, so we want to know that if it's worth to migrate to UVM?

What't the advantage or disadvantage between VMM and UVM, why we need to adopting UVM rather than VMM?

Wow, it's amazing that Sharon and Kathleen here. I'm a verification engineer from china, and the book is really great to read.