UVM is an extension of OVM and backward compatibility is being strongly encouraged. That's fine for OVM users, but what motivation is there for VMM users to make the switch? Accellera already offers an interoperability standard for OVM/VMM. VMM base class libraries are written in SystemVerilog and can run on multiple simulators (with minor adjustments for unsupported SV features). There's good reason for OVM users to adopt UVM; the changes are minimal and OVM development is being sunset. Converting from VMM to UVM is a bigger leap and the ROI isn't clear. In order to unite the OVM and VMM users, the burden of conversion needs to be shared. If VMM-RAL was adopted as the base register package, it would offer some consistency for existing VMM users and be a good gesture to show that UVM isn't simply the next version of OVM.