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vishal.jain

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Files posted by vishal.jain

  1. Cadence UVM_RGM2.7.5 release

    UVM_RGM2.7.5 is the UVM version of the Cadence Register and Memory package that has been tested by multiple users on all major commercial simulators. 
    Bug Fixed:  


    Fixed issue with backdoor read for special read fields  Fixed issue with sync for special read fields Guarded exclude names with empty string match Fixed filtering by breaking immediately when condition matches
    Walking one built-in-seq did not create the regOp when writing. Mode based register enum field macro having wrong case statement Typo in DPI file (vhpiHandleT changed to vpiHandle) Check for address overlap for indirect / shared and mode-based corrected
    Modified the burst rd-wr testcase to have response Include / exclude addresses, get_config_object issue with reference handle pass  
    Enhancements: Added support for mode based registers having separate storage Added stand-alone examples for mode-based registers Fixed the typo in sequence macro file when it error Shared register treated as RW register when filtering using condition Shared-indirect register not handled correctly by built-in-sequences Missing clone bit in get_config_object of address_range in sequence library

    1,744 downloads

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  2. Cadence UVM_RGM2.6.1 release

    UVM_RGM2.6.1 is the UVM version of the Cadence Register and Memory package that has been tested by multiple users on all major commercial simulators.
    Bug Fixed:

    Fixed issue with syncing to VHDL. Register overlap check error with end address Backdoor read of register fields was not properly masked Filtering of registers having unknown value is now only for rd_all regs seq Enhancements:
    Allowed backdoor write to read-only fields Allowed register's reset value over-ride using plusArgs Added register array delete at the end of built-in-seq Added support field-level backdoor access for shared register Modified shared_reg_backdoor example and added ipxact file Removed all uvm deprication warnings from examples Added support for VHDL backdoor std_ulogic_[ports |signals | vectorSignals] Modified all headers of XML files to get schema from http Added objection to built-in-sequences Added a global field to mask-out comparison of all non-read-write fields Added a global field to enable warning when accessed address is outside container

    1,197 downloads

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