Jump to content

saad

Members
  • Content Count

    3
  • Joined

  • Last visited

About saad

  • Rank
    Member

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. I mean like an output register which can save a value for one clock cycle and than put the value on its output if the enable signal is high. and what do you mean by we can model a register in anyway we want? or do you mean if I make SC_THREAD sensitive to clock pos edge and than get an enable signal as an input to SC_THREAD and make an if condition if enable signal is high output = input than it will behave like a register and yes I am working with non-synthesizable high level model and just running systemC from command line as presented in forte design system series on youtube.
  2. Thank you very much for your helpful answer. Now I am trying to use SC_THREAD but confuse in one thing that how can I model a register in SC_THREAD. Because I know that if we declare a variable in SC_CTHREAD as sc_signal than it is modeled as a register but how can I do that in SC_THREAD. I can make SC_THREAD sensitive to a positive clock edge and a reset but I do not think that will model the registers where I want them.
  3. I am trying to model a direct mapped cache and there is main memory module which is an SC_CTHREAD and main memory state machine which also SC_CTHREAD. I am experiencing one clock cycle delay when I write to an output from main memory and read it from main memory state machine. But i thought i could read in the same clock cycle isnt it true?
×