I mean like an output register which can save a value for one clock cycle and than put the value on its output if the enable signal is high.
and what do you mean by we can model a register in anyway we want? or do you mean if I make SC_THREAD sensitive to clock pos edge and than get an enable signal as an input to SC_THREAD and make an if condition if enable signal is high output = input than it will behave like a register and yes I am working with non-synthesizable high level model and just running systemC from command line as presented in forte design system series on youtube.