dennisb Posted September 5, 2012 Report Share Posted September 5, 2012 September 13, 2012 Online Mentor Graphics Seminar 9:00 AM - 10:00 AM US/Pacific Convert to Local Time Register Overview Many hardware blocks are designed to interact with software using memory mapped registers. In the final implementation, the system level software, running on a CPU, reads and writes these registers via a bus interface on the hardware block. With UVM sequence based stimulus, accesses to these registers are made via a bus agent, sometimes in a directed way that emulates software accesses, sometimes using constrained random stimulus. This seminar describes a technique in which C stimulus can be applied to the DUT via an existing UVM testbench that contains one or more bus agents. The approach used is to add a C register read/write API for use by C source code, which calls tasks in a SystemVerilog package via the SystemVerilog DPI mechanism to enable the C to make register accesses via the UVM testbench bus agents. The API enables c code to be compiled and then run on the host workstation during the simulation of a UVM environment. What You Will Learn Review of a register-level testbench architecture Tradeoffs associated with C stimulus alternatives How to extend your environment to accept C stimulus How to use the c_stimulus_pkg to use C code as stimulus in your environment Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.