Learning SystemC

[sprl111]

After endless frustration with the AMD Vitis (Unified? HLS?. even that is confusing) together with no AMD support, I'm looking at other alternatives for complex system architecture, design and simulation.  I've done a lot of FPGA HDL (VHDL and some Verilog) work over the past decade but some things just become intractable on an HDL level.  I'm comfortable with C++ and I'm reading Black, Donovan, et al.  So, it seems that SystemC is capable of the very abstract high level down to cycle/clock accurate logic.  So, what tools do people use for SystemC?  Simulation seems pretty straight forward as it seems that just about any C++ compiler will work but what about synthesis targeting AMD or Intel FPGAs?  Thanks.

[Matt Bone]

Focusing specifically on your question about synthesis,

You can find a large list of high-level synthesis tools here:
  https://en.wikipedia.org/wiki/High-level_synthesis

For synthesizing SystemC, all options are commercial ($$) tools that can target ASIC or FPGA:
  https://eda.sw.siemens.com/en-US/ic/catapult-high-level-synthesis/
  https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html
  https://www.nec.com/en/global/prod/cwb/index.html

For synthesizing C/C++ targeting FPGA, Intel/Altera and AMD/Xilinx have their own solutions:
  https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html
  https://www.xilinx.com/products/design-tools/vitis/vitis-hls.html

Note that Vitis deprecated support for SystemC synthesis in 2020 and is limited to C/C++ input.

 

[sprl111]

Thank you.