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Error: complete binding failed: port not bound. the port is the seq_item_port of a slave driver

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In my verification environment, there is a driver operating as a slave mode without the need for a seq_item_port, so its  seq_item_port is not connect to seq_item_export of the sequencer. However, when running the test, an error occurs as indicated in the title.  I used to connect seq_item_port only when the driver is in a master agent in systemverilog. look like it is mandatory to connect every seq_item_port of drivers?

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Hi Jerome,

According to the standard, a uvm_driver shall have a seq_item_port and an rsp_port. What is your use case for including a uvm_driver that is not fetching sequences from a sequencer? Probably you should derive your own "driver" component from uvm_component and only add the ports that you need?



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