Jerome Posted February 21 Report Share Posted February 21 In my verification environment, there is a driver operating as a slave mode without the need for a seq_item_port, so its seq_item_port is not connect to seq_item_export of the sequencer. However, when running the test, an error occurs as indicated in the title. I used to connect seq_item_port only when the driver is in a master agent in systemverilog. look like it is mandatory to connect every seq_item_port of drivers？ Quote Link to comment Share on other sites More sharing options...
Bas Arts Posted February 21 Report Share Posted February 21 Hi Jerome, According to the standard, a uvm_driver shall have a seq_item_port and an rsp_port. What is your use case for including a uvm_driver that is not fetching sequences from a sequencer? Probably you should derive your own "driver" component from uvm_component and only add the ports that you need? -- Bas Quote Link to comment Share on other sites More sharing options...
Jerome Posted February 22 Author Report Share Posted February 22 Hi Bas, thanks for your replying. I am learing some coding parctices from the examples. your answer has broaden my thinking. BR Jerome Quote Link to comment Share on other sites More sharing options...
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