Risto Posted May 10 Report Share Posted May 10 Hello, I've been using SystemRDL for the last few months, and although I think that the language has a lot of potential, I feel like it is lacking some features. One of the most surprising missing features for me is $clog2 operator from Verilog. It is really a common thing to have your parameter be a number and have a field that is adjusted to the width to fit that number. One way I get around it is by defining a SV style macro and use it like this: `define CLOG2(VAL) \ (((VAL) <= 1) ? 0 : \ ((VAL) <= 2) ? 1 : \ ((VAL) <= 4) ? 2 : \ ((VAL) <= 8) ? 3 : \ ((VAL) <= 16) ? 4 : \ ((VAL) <= 32) ? 5 : \ ((VAL) <= 64) ? 6 : \ ((VAL) <= 128) ? 7 : \ ((VAL) <= 256) ? 8 : \ .................. : \ 0 This works fine but still feels like this should be a part of the language. Are you taking feature requests, is it foreseen to have another revision of the standard in the future? If so I would have more feature requests that I would like to be implemented. Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.