Risto Posted May 10, 2023 Report Posted May 10, 2023 Hello, I've been using SystemRDL for the last few months, and although I think that the language has a lot of potential, I feel like it is lacking some features. One of the most surprising missing features for me is $clog2 operator from Verilog. It is really a common thing to have your parameter be a number and have a field that is adjusted to the width to fit that number. One way I get around it is by defining a SV style macro and use it like this: `define CLOG2(VAL) \ (((VAL) <= 1) ? 0 : \ ((VAL) <= 2) ? 1 : \ ((VAL) <= 4) ? 2 : \ ((VAL) <= 8) ? 3 : \ ((VAL) <= 16) ? 4 : \ ((VAL) <= 32) ? 5 : \ ((VAL) <= 64) ? 6 : \ ((VAL) <= 128) ? 7 : \ ((VAL) <= 256) ? 8 : \ .................. : \ 0 This works fine but still feels like this should be a part of the language. Are you taking feature requests, is it foreseen to have another revision of the standard in the future? If so I would have more feature requests that I would like to be implemented. Quote
Richard Weber Posted May 10, 2023 Report Posted May 10, 2023 Hello Risto, The $clog2() function has been part of IP-XACT since the 2014 version. It was my intention to add the same IP-XACT System Verilog expression capability to SystemRDL. Due to time and resource constraints the committee voted to implement a smaller subset of the System Verilog expression features for SystemRDL 2.0. I agree that $clog2() should be added to the next version of SystemRDL. rskvprd 1 Quote
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