sc_vector<sc_vector<>> issues - issues related to binding a vectored port

[Bryan]

Hello all,

I am building a SystemC model for a project and running into a wall attempting to utilize a sc_vector of sc_vectors for connecting ports. My project is modeling hardware behavior of a design in which I have a few levels of hierarchy, and as I move up the hierarchy, I am assembling a vector from individual signals. At the top of the hierarchy, I need to bind a vector from the middle hierarchy into a vector of vectors at the top.

I have created an ultra-simplified testcase of this which demonstrates the issue I run into. I compile cleanly (with SystemC 2.3.4), but my runtime output fails with the following output. If it matters, I am compiling in a Linux environment with with g++ version 8.3.0.

        SystemC 2.3.4-Accellera --- Feb  9 2023 17:55:01

Warning: (W807) sc_vector::bind called with empty range: target `tophier.midhier0.test_vec_mid' (sc_vector) empty destination range given
In file: ../../../src/sysc/utils/sc_vector.cpp:119

Warning: (W807) sc_vector::bind called with empty range: target `tophier.midhier1.test_vec_mid' (sc_vector) empty destination range given
In file: ../../../src/sysc/utils/sc_vector.cpp:119

Warning: (W807) sc_vector::bind called with empty range: target `tophier.midhier2.test_vec_mid' (sc_vector) empty destination range given
In file: ../../../src/sysc/utils/sc_vector.cpp:119

Warning: (W807) sc_vector::bind called with empty range: target `tophier.midhier3.test_vec_mid' (sc_vector) empty destination range given
In file: ../../../src/sysc/utils/sc_vector.cpp:119

Starting simulation...

Error: (E109) complete binding failed: port not bound: port 'tophier.midhier3.test_vec_mid_3' (sc_out)
In file: ../../../src/sysc/communication/sc_port.cpp:235

I do not profess to be very experienced with C++ / SystemC in general, but I have created a few SystemC projects (and am quite experienced as a digital design engineer). I have used regular sc_vectors in the past with success, but I haven't tried to create a vector of vectors.

There may be a better way to do this. A quick description of my testcase:

• at the bottom-hierarchy, I create a simple 1-bit signal (sig).
• at the middle-hierarchy, I instantiate multiple bottom-hierarchy modules and want to create a vector of the sig signals into test_vec_mid.
• at the top-hierarchy, I instantiate multiple middle-hierarchy modules and then want to assemble a 2-dimensional array (vector) of the test_vec_mid signals.

In my actual design, I will use that 2D array to redistribute the bits from the vector.

Below I will paste my code segment, and if easier, here is a link to the EDAPlayground version of the code. It gives the same errors I see in my system. 

Link to testcase

One more note - I would prefer to use a bool for the datatype at the bottom-hierarchy, but the sc_vector assembly at the top gives a different error. The bool type doesn't have some method the vector assembly is looking for, so I moved to the sc_bv<1>. If there is an easy solution to that, I would be all ears.

Finally, I am compiling with -DSC_INCLUDE_DYNAMIC_PROCESSES which was necessary based on the extensive Googling I have done before creating this testcase and posting here (my first post).

Thanx to anyone who can offer a solution to this for me!

#include <systemc>
using namespace sc_core;
using namespace sc_dt;

#include <iostream>
using namespace std;

typedef sc_bv<1>    BaseType;

struct BottomHier : sc_module
{
public:
    sc_in<bool>                     clk{"clk"};
    sc_out<BaseType>                sig{"sig"};

    BottomHier(sc_module_name name) : 
        sc_module(name)
    {
        SC_HAS_PROCESS(BottomHier);
        SC_THREAD(do_work);
            sensitive << clk.pos();
    }

    void do_work() {
        sig.write(0);

        while (1) {
            sig.write(rand() % 2);
            wait();
        }
    }
};

struct MidHier : sc_module
{
public:
    sc_in<bool>                     clk{"clk"};
    sc_vector<sc_out<BaseType > >   test_vec_mid;

    BottomHier*                     bottomhier[4];

    MidHier(sc_module_name name) : 
        sc_module(name),
        test_vec_mid("test_vec_mid", 4)
    {
        for (uint i=0; i<4; i++) {
            string str = "bottomhier" + to_string(i);
            bottomhier[i] = new BottomHier(str.c_str());

            bottomhier[i]->clk(clk);
            bottomhier[i]->sig(test_vec_mid[i]);
        }
    }
};

struct TopHier : sc_module
{
    sc_clock                                        clk{"clk", 10, SC_NS};
    sc_vector<sc_vector<sc_signal<BaseType > > >    test_vec;

    static sc_vector< sc_signal< BaseType > >* element_vector_creator(size_t size, const char* name, size_t) {
        return new sc_vector< sc_signal< BaseType > >( name, size );
    }

    MidHier*                    midhier[4];

    TopHier(sc_module_name name) : 
        sc_module(name), 
        test_vec("test_vec", 4)
    {
        for (uint i=0; i<4; i++) {
            string str = "midhier" + to_string(i);
            midhier[i] = new MidHier(str.c_str());

            midhier[i]->clk(clk);
            midhier[i]->test_vec_mid(test_vec[i]);
        }
    }
};

int sc_main(int argc, char *argv[])
{
    TopHier tophier("tophier");

    cout << endl << "Starting simulation..." << endl << endl;
    sc_start(200, SC_NS);
    cout << endl << "Simulation complete..." << endl;

    return 0;
}

 

 

 

[Andy Goodrich]

Correct me if I am wrong, but the statement:

sc_vector<sc_vector<sc_signal<BaseType > > >    test_vec;

will create a vector, test_vec, containing another vector whose elements would be type sc_signal<BaseType>, but that inner vector does not have any elements. The sc_vector() constructor without any arguments will be called for the inner sc_vector instances, that will call sc_vector_base() with no  arguments, and no  object instances will have been placed in the vector.