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Can we use systemc models for formal verification

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Hi Deepak,


Could you be more specific on "formal verification"? Do you want to execute property checking / assertions / .... on the SystemC model itself? Do you want to use the SystemC model in an equivalence checking setup with RTL or gate level? Do you have another use case?

As far as I'm aware, commercially available formal verification tooling does not work (directly) with SystemC so, depending on your use case, you might need to synthesize the model.

Perhaps the Verification Academy is a good starting point for you?



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