dennisb Posted March 20, 2012 Report Share Posted March 20, 2012 See go.mentor.com/uvm-exp for more information on Mentor's UVM Express web seminar and to register. Date: 29 March 2012 Time: 8:00 AM - 9:00 AM US/Pacific (Convert to Local Time) Overview UVM Express is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. The techniques include raising the abstraction level of tests, writing tests using BFM function and task calls, adding functional coverage, and adding constrained-random stimulus generation. The UVM itself is a powerful class library and associated usage guidelines for creating reusable transaction-level verification environments and components. Unfortunately for many teams, UVMâ€™s reliance on the object-oriented programming (OOP) features of SystemVerilog and advanced features means that the barrier to adoption of UVM is simply too high. UVM Express makes it easier to adopt key pieces of UVM in a much more straightforward manner, while leaving open the opportunity to adopt full UVM in the future. What You Will Learn How to raise the abstraction level of your test by structuring your environment to use Bus Functional Models (BFMs) using tasks in interfaces to facilitate test writing How to add functional coverage to an existing BFM-based testbench to measure the quality of your existing tests How to add constrained-random stimulus generation to an existing BFM-based testbench to improve the productivity of the test write and improve the overall quality of your test environment. How to instantiate and configure VIP components to simplify the adoption of functional coverage and constrained-random stimulus How to move from initial adoption with UVM Express to a full UVM-based environment Quote Link to comment Share on other sites More sharing options...
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