Maciej Piechotka Posted May 30, 2017 Report Share Posted May 30, 2017 I'm programming against fixed interface but I am afraid I am beginner in SystemC. I'm trying to limit myself to a synthesable subset. This particular part is meant to be reusable interface consisting of 3 lines - data (for data), valid (notifying that data is valid) and ready (denoting that system is capable of receiving). Data is considered transferred when valid and ready signal are both asserted in a single clock cycle. I keep running into troubles as SystemC is reading data from previous cycle sometimes. I don't know what the correct way is of fixing this without loosing modularity. axis_lite.h axis_lite_test.cpp Quote Link to comment Share on other sites More sharing options...
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