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Maciej Piechotka

Deasserting signals in a single clock cycle

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I'm programming against fixed interface but I am afraid I am beginner in SystemC. I'm trying to limit myself to a synthesable subset. This particular part is meant to be reusable interface consisting of 3 lines - data (for data), valid (notifying that data is valid) and ready (denoting that system is capable of receiving). Data is considered transferred when valid and ready signal are both asserted in a single clock cycle.

I keep running into troubles as SystemC is reading data from previous cycle sometimes. I don't know what the correct way is of fixing this without loosing modularity.

axis_lite.h

axis_lite_test.cpp

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I would advice using SC_CTHREADS both for DUT and Testbench when debugging signal-level protocols. This will save you from race conditions (everything will be synchronized to common clock signal)

This particular protocolĀ is implemented inside SystemC examples, you can check usage example in

systemc_root/examples/sysc/2.3/sc_rvd/*

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