kybiss Posted September 23, 2016 Report Share Posted September 23, 2016 Hi, I am trying to write a simple bus-based architecture. But I cant write the arbiter module. There are two processes M1 and M2. The arbiter allocates a different time slot for M1 or M2, so that they are both granted access to the bus at different times. Here is the m_bus : #define _CRT_SECURE_NO_WARNINGS #include"systemc.h" SC_MODULE(m_bus) { sc_in<char> char_in1; sc_in<char> char_in2; sc_in<bool> selector; sc_out<char> char_out; void prc_m_bus(); SC_CTOR(m_bus) { SC_METHOD (prc_m_bus); sensitive << char_in1 << char_in2 << selector; } void m_bus :: prc_m_bus(){ if (selector == 0) { char_out = char_in1; cout << "change_case" << endl; } else if (selector == 1) { char_out = char_in2; cout << "filter" << endl; } else; } }; Is there anyone who can help me for writing arbiter? Quote Link to comment Share on other sites More sharing options...
vijay.franklin Posted October 21, 2016 Report Share Posted October 21, 2016 You would need a clock port that is hooked up to a clock generator -- which would enable the actual progression of simulation of time. Now, when you add in that, I would model the algorithm somewhere along the lines of In pseudo code: --- would never compile //! resourcesSC_METHOD --> hook_method_1 (sensitive to char_in1); SC_METHOD --> hook_method_2 (sensitive to char_in2); SC_THREAD ---> process_queue SC_METHOD --> process_method (sensitive to process_event) queue <char_data> //!processes hook_method_1 (){ queue.push_back(char_in1) //! always enter data in the last position notify process_event ( clean this with atomic signalling to avoid multiple unwanted triggers) } hook_method_2 () { wait for delta cycle //! in case char_in1, 2 changes in same clock, give more priority to char_in1 queue.push_back(char_in2) notify process_event ( clean this with atomic signalling to avoid multiple unwanted triggers) } process_method(){ wait for process event schedule all elements in queue by notifying "float in sc_out event" with appropriate delays between bus transitions. ie, if there are two requests in queue and you want the data to be valid for two cycles and other for three cycles, notify the "float in sc_out event" with appropriate delays. } process_queue(){ while(1){ wait(for "float in sc_out event") while(there are elements in queue ){ * get top most char from queue * put the data from queue into the sc_out * delete the data from queue //! as already sent out } } } Quote Link to comment Share on other sites More sharing options...
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