avikbose1145 Posted July 28, 2016 Report Share Posted July 28, 2016 Dear all, can any one give me some guidance...I want to design a processing core like any general purpose processor and want it to execute real time program code...like it will have its own instruction set format and it will execute the target code generated for it...using systemc what are the footsteps i need to follow...i will be obliged highly for your help Quote Link to comment Share on other sites More sharing options...
Roman Popov Posted July 28, 2016 Report Share Posted July 28, 2016 Do you want it to be synthesizable? Or you just need an ISA simulator? Quote Link to comment Share on other sites More sharing options...
avikbose1145 Posted July 29, 2016 Author Report Share Posted July 29, 2016 Dear Roman sir, i wish to design an ISA (instruction set simulator). I think for synthesizable simulator i need to implement it on a gate level which for now i do not need. Will be obliged for your help Quote Link to comment Share on other sites More sharing options...
Roman Popov Posted July 29, 2016 Report Share Posted July 29, 2016 Dear Roman sir, i wish to design an ISA (instruction set simulator). I think for synthesizable simulator i need to implement it on a gate level which for now i do not need. Will be obliged for your help In that case you don't need SystemC. You can write your ISA simulator in pure C++. First learn your ISA, then write a CPU state model (registers), then write instruction parser (decoder and interpreter). Quote Link to comment Share on other sites More sharing options...
avikbose1145 Posted July 29, 2016 Author Report Share Posted July 29, 2016 In that case you don't need SystemC. You can write your ISA simulator in pure C++. First learn your ISA, then write a CPU state model (registers), then write instruction parser (decoder and interpreter). Roman sir, i am working on multicore network on chip where i need to test the network as well as the processing time of a thread...i need an event driven simulation which includes both the computation and communication...in that case can i design the processing core using systemc...because in c++ i can not accomplish the cycle accurate processing time...need your precious suggestions. Quote Link to comment Share on other sites More sharing options...
Roman Popov Posted July 29, 2016 Report Share Posted July 29, 2016 Roman sir, i am working on multicore network on chip where i need to test the network as well as the processing time of a thread...i need an event driven simulation which includes both the computation and communication...in that case can i design the processing core using systemc...because in c++ i can not accomplish the cycle accurate processing time...need your precious suggestions. In that case you will need to learn SystemC TLM modeling. You can still write your CPU model in pure C++ but provide some hooks for event notifications and cycle count tracking. Unfortunately, (In my experience) there is no good learning material for beginners. You can check Duolos TLM tutorial: https://www.doulos.com/knowhow/systemc/tlm2/tutorial__1/ On GreenSocs Git there are examples of integrating CPU models with SystemC/TLM https://git.greensocs.com/explore/projects Quote Link to comment Share on other sites More sharing options...
avikbose1145 Posted July 29, 2016 Author Report Share Posted July 29, 2016 In that case you will need to learn SystemC TLM modeling. You can still write your CPU model in pure C++ but provide some hooks for event notifications and cycle count tracking. Unfortunately, (In my experience) there is no good learning material for beginners. You can check Duolos TLM tutorial: https://www.doulos.com/knowhow/systemc/tlm2/tutorial__1/ On GreenSocs Git there are examples of integrating CPU models with SystemC/TLM https://git.greensocs.com/explore/projects Thank you Sir Quote Link to comment Share on other sites More sharing options...
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