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Hello there, 

The simulation for my module stops at 55 ns. This might probably happen because of my driver. In GTKwave , am not able to view what is the input and output at 55(th) ns, since the simulation stops exactly stops at 55. 

How to keep the simulation time to be infinite or extend more so that I can also view the last set of inputs? 

I also tried deactivating the "sc_stop()" command, but no change was found. If so, what's the need of sc_stop() ?


Any help would be appreciated. :)


Thanks in advance.

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Hello Roman, 

sc_start command has been passed in my main module. But, still the simulation stops at exactly 55 ns, where all my inputs are finished driven. I would love to know , how to extend the simulation time even after all my inputs are driven.


Ok, I understood what you mean. Yes, looks like waveform will always end at the moment last signal change happened.


Here is my test:


SC_MODULE(test) {
sc_signal<bool> data{"data"};

SC_CTOR(test) {

void test_thread() {
data = true;
wait(1, SC_US);
data = false;
wait(1, SC_US);
data = true;
wait(1, SC_US);

int sc_main(int, char**) {

test test_inst{"test_inst"};

sc_trace_file *fp;

cout << "simulation finished at " << sc_time_stamp() << endl;
return 0;


At console I get:

simulation finished at 3 us


But in VCD there will be only 2 us of waveform trace.


I think is a bug/limitation of opensource SystemC. 

In commercial simulator (Synopsys VCS) I observe full waveform of 3 us.

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The VCD gets updated when a signal changes. So if there is no change after 2 us of any signal there is no reason to write to the VCD. What does VCS write to the VCD at 3 us?

yes, my mistake. I've looked into wrong dump.

VCS created two: wave.vcd produced by sc_trace has 2 us of waveform. And vpd dump created by VCS itself has 3 us. 


I'm not aware of VCD file format, but probably it makes sense to update VCD when simulation ends? In that case you will see what you expect: if you run simulation for 3 us you will have waveform of 3 us. Even if nothing has changed during last us..

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The basic logic of a VCD signal change is "write a timestamp, write signals which have changed". So if there is no change of any signal there would be no need to have a timestamp for 3 us. However, VCD does not forbid to have the same value written again for any signal (so that it gets an entry in the VCD although it has not changed since the last time). With this method you actually can have signal values for 3 us. So my guess would be that VCS dumps all signals at the simulation end.

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