Ahmed Posted November 13, 2012 Report Share Posted November 13, 2012 Hi every one, I am testing a bus fabric where several components are connected. I am replacing those components by Systemc models to reduce the simulation time. The bus fabric is the only rtl component. where the TB is in vhdl. The TB instantiate the Systemc components. I wonder if I want to connect a systemc component "instantiated by the TB" to another sysc component "buried inside other component instantiated by the TB" How can I do that using TLM without affecting the instantiator interface. Thanks, Ahmed Quote Link to comment Share on other sites More sharing options...
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