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UVM1.0, TLM2.0 and Functional Verification

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UVM1.0 attracted the attentions of many, and this was visible at the multiple sessions at DVCON. One of the features that is new to UVM is a partial implementation of TLM 2.0 (only SV to SV ports are supported). A few introductory sessions nicely covered the technical attributes of TLM2.0 standard. At the same time, many users came away confused from the sessions about the role of TLM2.0 in verification testbenches vs. modeling and what can be done today. I wrote a short technical blog to clarify the guidelines and Cadence position on this. Follow this link for the technical discussion:


-- Sharon

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