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SystemC and VHDL co-simulation


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I have used Modelsim to compare simulation results between a C model encapsulated in SystemC to its VHDL implementation, mostly with a GUI, for hardware verification.

I am trying to see how SystemC can be used for Software validation and/or regression testing using a SystemC testbench that has software modules, SystemC models, and VHDL HW modules when fidelity is needed. I am assuming the open-source SystemC simulator does not support VHDL natively so a VHDL simulator would be needed like modelsim.

What is the best way to use the SystemC open source simulation to make calls to a VHDL simulator like modelsim while reducing the license usage of modelsim?

Can you share your experience and lessons learned regarding mixed language sims?



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The easiest way would be to get a SystemC license for your Modelsim.


If this is not possible then there are the usual methods for interprocess communication. Probably the easiest method is to use sockets, you could use Tcl (force/when/examine) to modify your VHDL.


If you have Modelsim DE then you can use the FLI (VHDL C/C++) interface again with sockets (there are FLI sockets function). If you are under Linux you can try named pipes (I failed to make it work under Windows) and of course you could use simple text files,

Good luck!


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