Giuli0 Posted August 17, 2014 Report Share Posted August 17, 2014 So, I am still working on this memory code, and I am still having troubles... The memory module has some submodules: a decoder, and a sc_vector containing mem_cell modules. The mem_cell has two input ports: datain, and address_enable. Address_enable is connected to the output port of the decoder, while datain is directly connected to the datain port of the memory upper level module. According to my design, mem_cell is sensitive to both address_enable and datain. My problem is that this signals have different path lengths: address_enable, receiving its value from the decoder, needs an extra delta-cycle to get updated, compared to the datain signal, which comes directly from the memory port. So, when testing, I get unexpected results. I think there must be a simple and effective way to synchronize everything. Would it be correct to put some "delay modules" along the fastest paths, in order to synchronize? Are there any other soulutions? I think I shouldn't modify the submodules, which are neat and already succesfully tested. Quote Link to comment Share on other sites More sharing options...
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