Submodule synchronization

[Giuli0]

So, I am still working on this memory code, and I am still having troubles...

The memory module has some submodules: a decoder, and a sc_vector containing mem_cell modules. The mem_cell has two input ports: datain, and address_enable. Address_enable is connected to the output port of the decoder, while datain is directly connected to the datain port of the memory upper level module.

According to my design, mem_cell is sensitive to both address_enable and datain. My problem is that this signals have different path lengths: address_enable, receiving its value from the decoder, needs an extra delta-cycle to get updated, compared to the datain signal, which comes directly from the memory port. So, when testing, I get unexpected results. I think there must be a simple and effective way to synchronize everything. Would it be correct to put some "delay modules" along the fastest paths, in order to synchronize? Are there any other soulutions? I think I shouldn't modify the submodules, which are neat and already succesfully tested. 

 

[ralph.goergen]

Hi.

 

Many people use clocks for synchronisation.

 

Delay modules are very wrong in almost every case. 

Delta cycles represent signal runtime in actual hardware. In gerneral, signal runtime is not fully deterministic in real hardware. Hence, if the functionallity of your design depends on signal runtime, it may work in the model, but it will most likely not work in rael hardware.

 

Greetings

Ralph

[Giuli0]

Hi Ralph,

thanks for your reply. Actually, I fixed the problem using a delay module. I agree with what you said, but in my case, I am integrating a pre existing project with no clock, and i preferred to keep everything as close as possible to the initial interface. Now it works.

[ralph.goergen]

You should better think about your overall design, your submodules or the expected behavior of the memory module. 

Relying on delta cycle count or the evaluation order of processes in the same delta cycle is very bad modeling style. It leads to very fragile models. When you change the routing in one module, it can lead to erroneous behavior in another module. Changes to the routing or adding additional channels/signals should not change the actual behavior of your design.