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Hi Guys

In one of my scenario, the initiator has to read a registers from traget memory map but only after when some process in target updated this.

So I can either poll this register to know when  it is updated and read it when it is updated. Here I need to poll this register so this is not a good practice.

The other soln is to just call b_transport with read command and in target side wait till this register gets updated. Is this the right approach ?

Is there some other way to achive this ?

 

Thanks

RahulJn

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What is the "Initiator" here? Is it emulating a processor model (and can, perhaps, execute the embedded software as well)? Or is it a DMA agent of a peripheral? In either case, what is the hardware behavior? Does the initiator poll the value of the register until it detects the register has been updated?

 

Also, what is the behavior on the target/slave side? If the target "blocks the read until the register gets updated", the behavior corresponds to a "slave device introducing bus wait cycles until the register gets updated". Is this the behavior of the real hardware? Note that, depending on how the bus is modeled, if the slave blocks the read, it can potentially block other masters on the bus as well. That side-effect may not be something you want to introduce.

 

In real H/W, if polling is costly, the design would have provisioned for an interrupt from the target/slave when the register is updated. Perhaps you can model it the same way?

 

So, it is not easy to answer your question conclusively - it all depends on what you are trying to model.

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Hello Karthik

 

The initiator is simple TLM model which is writing/reading the memory map. It can be replaced with ISS in future.

In my initiator model I have separate thread for reading the updated value(other than normal read/write thread). As I have separate thread so even the read is blocked, the bus will still be accessible to others.

 

I can model this with an interrupt but in actual model there is no interrupt pin.

 

Given this situation andc onstraints, I am seeing no way other than blocked read.

 

Thanks

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Hello Karthik

 

The initiator is simple TLM model which is writing/reading the memory map. It can be replaced with ISS in future.

In my initiator model I have separate thread for reading the updated value(other than normal read/write thread). As I have separate thread so even the read is blocked, the bus will still be accessible to others.

 

I can model this with an interrupt but in actual model there is no interrupt pin.

 

Given this situation andc onstraints, I am seeing no way other than blocked read.

 

Thanks

If,

a. In real hardware there is no interrupt signal, and

b. The initiator can be replaced by an Instruction Set Simulator in future,

then, I would suggest to let initiator poll the register content in the target (with some delay between the polls).

 

Suppose the target blocks the initiator's read until the register gets updated - you'll run in to the following issues (as a sample):

a. When the initiator is replaced by ISS, the ISS executes S/W which might expect a completely different behavior from the target. This can lead to dead-locks.. for instance, if the S/W has a "poll_thread" that is polling the register, and a "worker_thread" that does something causing the target's register to get updated, it is very much possible that the changed behavior on the target side causes a dead-lock.

b. The target can hold the bus until the register gets updated. This can block other masters from accessing the bus - affecting the measured performance

c. The behavior above can again potentially lead to a dead-lock, if a DMA is required before the register can get updated (the DMA will be blocked until the bus is free, and the bus is busy until the register gets updated, the regsiter gets updated after the DMA happens).

 

In general, the SystemC model must be as smart as the RTL- but no further.

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