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TLM model with VHDL/Verilog

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Hi All,


I am new to TLM modeling and I have a question regarding usage of TLMs in co-simulation with HDL languages.


Does someone know how to use TLM model in let's say VHDL design?

For example, how to connect TLM model of an interconnect with other module in the design that are implemented in VHDL?

I understand this would require implementing full physical interface (such as AXI, AHB, OCP or any other) on TLM model itself in order to connect it to VHDL, but I am not sure what would be the proper place in TLM to implement physical interface.




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Hi Igor,

The way to connect your TLM to another module via a standard interface (e.g. AXI, etc.) really depends on the framework used to create the TLM.

OS-VVM is one such framework, and if you are using this, you would like to read the resources available at osvvm.org or at synthworks.com.


If you are interested, I also have public classes available on VHDL-based TLM/BFM:



Feel free to drop me an email at: daniel [dot] kho [at] tauhop.com


Best regards,


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