iignjic Posted February 12, 2014 Report Share Posted February 12, 2014 Hi All, I am new to TLM modeling and I have a question regarding usage of TLMs in co-simulation with HDL languages. Does someone know how to use TLM model in let's say VHDL design? For example, how to connect TLM model of an interconnect with other module in the design that are implemented in VHDL? I understand this would require implementing full physical interface (such as AXI, AHB, OCP or any other) on TLM model itself in order to connect it to VHDL, but I am not sure what would be the proper place in TLM to implement physical interface. Thanks, Igor Quote Link to comment Share on other sites More sharing options...
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