Using TLM to implement communication between processor's pipeline and file register

[feron_jb]

Hello,

I'm developping a processor behavioural model using SystemC/TLM standard.

I try to make the result cycle-accurate.

I have some troubles for modelling the pipeline-file register communication with TLM. I want to to be able to write in a register but the new data must be available for a read only one clock cycle later (or 20ns later).

 

I could do this by implementing sockets in my pipeline and my file register modules, using the available generic payload, as my file register is addressed.

However, some of my registers are defined as structure containing boolean in order to read or write easily configuration or status flags. If I want to read or write the complete register, I have functions concatenating boolean flags into or extracting boolean flags from short integers.

 

Using TLM, how could I easily write a particular flag in a register with a delay?

Is it possible to add a mask to the generic payload or to delay the write in the boolean structure?

 

If someone has a solution, can he illustrate it with an example?

If necessary, I can try to illustrate my problem with an example, do not hesitate to ask!

 

Thank you!

[feron_jb]

I could finally make it using TLM docmentation (the IEEE 1666 standard might be useful).

I had to implement a TLM transaction extension to fit the particular needs of some transactions between the pipeline and the file register.

Useful examples for TLM transaction extensions are provided in a document from the university of Munich.

Finally, the Doulos examples are also interesting (but less interesting than the last one).

 

Hope this helped!

J-B