Datatypes - Interface SystemC - VHDL

[wsch]

Hi

I'm working in a project where I must connect a testbench SystemC with a Hardware described in VHDL.

So in VHDL side I have

a type:

TX_LEN_ARRAY is array (0 to 16-1) of std_logic_vector(16-1 downto 0);

In SystemC side I have

sc_core::sc_in<sc_dt::sc_lv<16>> tx_len_tg_wra[16];

I have encountered some errors. And so I wonder if the data types are equivalent?

Thanks

[ralph.goergen]

Short answer: No, they are not equivalent.

Longer answer:

1: Co-Simulation depends on the tool you are using. Without knowing the tool, it is hard to help you.

2: You declare two different things. In VHDL, assuming you have a port of the given type, you declare *one* port. The inner type of this port is an array of logic_vectors. In SystemC, you declare an array of ports, i.e. 16 ports. The inner type of each of them is sc_lv<16>.

3: I'm not sure if co-simulation supports things like that. AFAIK Modelsim does not support user-defined port types at the Co-simulation boundary (and your array is a user-defined type). And I think that arrays of ports are not supported as well (Modelsim matches the names of individual ports and array elements do not have actual names).

4: Minor issue: sc_logic/sc_lv and std_logic/std_logic_vector are not exactly the same. The first is 4-value logic with SystemC semantics, the second is 7-value logic, a resolved type and VHDL semantics.

Possible solution:

Have a look at the port type mapping rules of your co-simulation tool.

If user-defined types/multidimensional arrays are not supported, you can write a simple wrapper around your VHDL model.

In the wrapper, you can concat your array to a single 16 * 16 logic_vector and rearrange it in SystemC (Take care of the array directions). Or you replace the single port with 16 individual port of type logic_vector.

Greetings

Ralph

[wsch]

Thanks a lot. The solution works!

I'm using Modelsim 10.1c

[ralph.goergen]

In the Modelsim User's Manual, you can find a section about VHDL and SystemC Signal Interaction and Mappings. It explains the data type mappings, etc.

To match the foreign language module, you have to use the same interface (port names and directions) in both worlds.