wsch Posted March 4, 2013 Report Share Posted March 4, 2013 Hi I'm working in a project where I must connect a testbench SystemC with a Hardware described in VHDL. So in VHDL side I have a type: TX_LEN_ARRAY is array (0 to 16-1) of std_logic_vector(16-1 downto 0); In SystemC side I have sc_core::sc_in<sc_dt::sc_lv<16>> tx_len_tg_wra; I have encountered some errors. And so I wonder if the data types are equivalent? Thanks Quote Link to comment Share on other sites More sharing options...
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