ecco Posted June 20, 2013 Report Share Posted June 20, 2013 Consider the following signal: sc_signal<sc_lv<size> > aux; Suppose "size" is something passed to the module through the use of template parametrization. How can I set the value of this guy to 0b0000....0000 or 0b1111....111 ? In VHDL there is the OTHERS keyword: aux <= (OTHERS => '1'); What about systemC? How can I achieve the same effect? Quote Link to comment Share on other sites More sharing options...
ralph.goergen Posted June 20, 2013 Report Share Posted June 20, 2013 Hi. Achieving the full flexibility of VHDL aggregates is very hard in SystemC. But if only OTHERS is your goal, there are workarounds. If you know the length of aux, you can use the sc_lv constructor with initialization: sc_lv<7> tmp('1'); aux.write(tmp); A more general approach is to use a template function: template < int W > void init_lv(sc_signal_inout_if < sc_lv < W > > & sig, const char val) { sig.write( sc_lv<W>(val) ); } Greetings Ralph maehne and karandeep963 2 Quote Link to comment Share on other sites More sharing options...
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