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Module with variable number of ports


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The easiest solution is to use an sc_vector of ports (new in SystemC 2.3).

Here is a simple example:

SC_MODULE( module )
  // vector of ports
  sc_core::sc_vector< sc_core::sc_in<int> > in_vec;

  module( sc_core::sc_module_name, unsigned n_in )
    : in_vec( "in_vec" ) // set name prefix
    // delayed initialisation of port vector
    in_vec.init( n_in );


For some more examples and features of  sc_vector, have a look at the SystemC 2011 New Features presentation (part of SystemC 2.3.0 download archive), and/or the IEEE 1666-2011 standard, section 8.5.


Greetings from Oldenburg,



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