StuartSwan

Matchlib Examples Kit for Accellera Synthesis Working Group
Stuart Swan
Platform Architect
Siemens EDA
stuart.swan@siemens.com
Matchlib is a new open-source SystemC library originally developed by NVidia Research to enable digital hardware to be accurately and efficiently designed and verified at a high level of abstraction, leveraging commercial high level synthesis tools. Some of the key goals of Matchlib are to provide a highly configurable library of HW components that can be directly synthesized to HW with very high quality of results, and to enable very accurate performance simulation of these models in SystemC prior to synthesis, so that the overall design and verification effort is much more efficient.  Matchlib contains models for commonly used HW components such as AXI bus fabric components (routers, arbiters, etc), network on chip components, banked memories, crossbars, etc.
Matchlib is being actively used by hardware design teams in both industry and academia for advanced hardware design projects, and multiple tapeouts from different groups have occurred for chips that have been almost entirely designed with Matchlib.
The recommended location to access the kit is this github link below:
https://github.com/Stuart-Swan/Matchlib-Examples-Kit-For-Accellera-Synthesis-WG
On-going updates to the kit occur in the above github repository.
(Downloads from the Accellera website may not work on certain browsers, and the download from the Accellera website is now out of date.)
A video from NVidia Research on Matchlib is here:
https://www.youtube.com/watch?v=n8_G-CaSSPU
This kit contains a representative set of Matchlib examples and fully self-contained source files and scripts so that the examples can be built and run on any linux compatible system with no other required software. All contents of the kit are open source.
Matchlib training slides are available here:
https://github.com/Stuart-Swan/Matchlib-Examples-Kit-For-Accellera-Synthesis-WG/blob/master/matchlib_examples/doc/matchlib_training.pdf
 

Matchlib: A New Open-source Library to Enable Efficient Use of High Level Synthesis
Stuart Swan
Platform Architect
Mentor, A Siemens Business
stuart_swan@mentor.com
 
Note: This download is now obsolete. The updated download can be accessed here:
https://forums.accellera.org/files/file/127-matchlib-examples-kit-for-accellera-synthesis-working-group/
 
 
Matchlib is a new open-source SystemC library developed by NVidia Research to enable digital hardware to be accurately and efficiently designed and verified at a high level of abstraction, leveraging commercial high level synthesis tools. Some of the key goals of Matchlib are to provide a highly configurable library of HW components that can be directly synthesized to HW with very high quality of results, and to enable very accurate performance simulation of these models in SystemC prior to synthesis, so that the overall design and verification effort is much more efficient.  Matchlib contains models for commonly-used HW components such as AXI bus fabric components (routers, arbiters, etc), network on chip components, banked memories, crossbars, etc.
Matchlib is being actively used by hardware design teams in both industry and academia for advanced hardware design projects, and multiple tapeouts from different groups have occured for chips that have been almost entirely designed with Matchlib.
A video from NVidia Research on Matchlib is here:
https://www.youtube.com/watch?v=n8_G-CaSSPU
This kit contains a representative set of Matchlib examples presented at Accellera SystemC Evolution Day 2020 and fully self-contained source files and scripts so that the examples can be built and run on any linux compatible system with no other required software. All contents of the kit are open source.

STMicroelectronics, ARM and Cadence Improve Tool and Model Interoperability with Three Joint Contributions to Accellera Systems Initiative
Proposed Interfaces for Interrupt Modeling, Register Introspection and Modeling of Memory Maps Enable Third-Party Model and Tools Markets
Geneva, Switzerland, Cambridge, UK, San Jose, California, July 29, 2013 -- STMicroelectronics, ARM and Cadence Design Systems, Inc. today announced three new contributions to the SystemC Language Working Group of the Accellera Systems Initiative. This collaboration will further increase model and tool interoperability for electronic system-level (ESL) design at the transaction-level.
The joint work includes new interfaces for interrupt modeling, which allow seamless integration of models from different companies; application programming interfaces for register introspection that enable tool interoperability to seamlessly display and update register values; and new approaches for memory-map modeling that improve users’ productivity during debugging of virtual platforms for hardware/software multicore systems. The contributions consist of fully working application programming interfaces (API) and implementations, as well as documentation and examples, released under an Apache 2.0 open-source license and available online at http://forums.accellera.org/files/.
“These new interfaces are crucial to strengthening the ESL ecosystem. As a step towards interoperability driven by ST, ARM and Cadence, these proposed standards dramatically reduce risks and efforts associated with the integration of virtual prototypes. Eliminating the need for adapters will increase virtual prototype simulation performances, enable sooner and faster hardware-software integration, and therefore improve product time-to-market,” said Philippe Magarshack, executive vice president, Design Enablement & Services, STMicroelectronics.
“Cadence has worked closely with ST, ARM and other partners to develop these open standards proposals,” said Stan Krolikoski, distinguished engineer, Cadence. “Adoption of these proposed standard interfaces in virtual prototyping solutions will enable the expansion of the ESL ecosystem and provide added value through interoperability to users.”
“The Accellera TLM 2 standard has been very important in enabling an ecosystem of models that can be integrated into SystemC virtual prototypes,” said John Goodenough, vice president of Design Technology and Automation, ARM. “By addressing a key gap in the model-to-model interface and by enhancing tool integration, these proposed contributions further help in ensuring virtual prototypes can be predictably and consistently integrated.”
"With the growing adoption of virtual prototypes for early software development, it is important to continue to simplify their creation while adding value for users,” said Yatin Trivedi, director, standards and interoperability at Synopsys. “As a market leader in virtual prototyping, we welcome contributions and discussions that help to advance the Accellera SystemC TLM standard."
“We look forward to working together and collaborating in the Accellera Systems Initiative SystemC Language Working Group to advance the needs for improved virtual prototyping model and tool interoperability,” said Shabtay Matalon, ESL market development manager from Mentor Graphics Corporation. “The initial open source contributions serve as a good catalyst to start the process of addressing and refining these pressing standards challenges.”
The first technical proposal addresses the need for better interoperability among SystemC TLM (Transaction Level Modeling) models and proposes a standard interface to model interrupts and wires at the Transaction Level. This will enable seamless integration of models from different companies with standardized memory-mapped connections, further enhancing the growth of a market for third-party TLM models.
The second proposal defines a standard interface between models and tools to support register introspection, enabling tools to seamlessly display and update register values. This interface works in a mix of different user-defined register classes to support platforms integrating heterogeneous models from various model providers. This capability is a key enabler for integration and debug of embedded software on pre-silicon virtual prototypes.
The third proposal introduces an approach to reconstruct system memory maps as seen from initiators, enabling ESL tools to support hardware/software debug on complex virtual platforms, for which understanding of the memory maps is instrumental. It addresses the challenge that memory maps depend on the interconnection of models and as a result each system initiator might have its own view.
With these new contributions, ST, ARM and Cadence expect the integration of SystemC models in virtual prototypes will be significantly improved for all users, enabling the models’ quick and efficient deployment. In addition, standard interfaces between models and tools will extend hardware/software integration and debug capabilities using appropriate tools.
Within the Accellera Systems Initiative, ARM, Cadence, and ST plan to work with other companies to refine and fully standardize these proposals.

This contribution contains a small, working example that demonstrates a general purpose, scalable approach for integrating UVM-SV and UVM-e models with SystemC TLM2 models.
Please see the PACKAGE_README.txt file and the uvm_tlm2_integration.pdf slides within thekit for further information on this example.
Full source code and run scripts are provided within the kit.