VanTeo

I just saw the new features in systemc-2.3.1a, they helped me solve this problem SC_CTHREAD(Fetch, clk.pos()); Fe = sc_get_current_process_handle(); SC_CTHREAD(Decode, clk.pos()); De = sc_get_current_process_handle(); SC_CTHREAD(EvaluateAddress, clk.pos()); Ev = sc_get_current_process_handle(); SC_CTHREAD(FetchOperands, clk.pos()); FeO = sc_get_current_process_handle(); SC_CTHREAD(Execute, clk.pos()); Ex = sc_get_current_process_handle(); SC_CTHREAD(Store, clk.pos()); St = sc_get_current_process_handle(); sc_process_handle Fe; sc_process_handle De; sc_process_handle Ev; sc_process_handle FeO; sc_process_handle Ex; sc_process_handle St; void Fetch() { while(true); wait(1); ... Fe.disable(); De.enable(); } void Decode() { while(true); wait(2); ... De.disable(); Ev.enable(); } void Evaluate() { while(true); wait(3); ... Ev.disable(); FeO.enable(); } void FetchOperands() { while(true); wait(4); ... FeO.disable(); Ex.enable(); } void Excute() { while(true); wait(5); ... Ex.disable(); St.enable(); } void Store() { while(true); wait(6); ... St.disable(); Fe.enable(); }

Becasue I am modeling a CPU, I have threads: Fetch, Decode, EvaluateAddress, FetchOperands, Execute, Store. I want to each thread will run in one clock cycle, the Fetch thread will run in first one clock cycle (sensitive by clock posedge) then will suspend and Decode thread will run after (in one clock cycle too), and the next wil be EvaluateAddress, FetchOperands, Execute, Store .... I don't know how to do it. Please help me. Regard, Huy

Hi, I have 6 thread s1, s2, s3 and I want to that these thread each take one clock cycle. Thread s1 is sensitive at first clock posedge and run in one clock cycle, s2 is sensitive at sencond clock posedge and run in one clock cycle, s3 is sensitive at third clock posedge and run in one clock cycle. Regard, VanTeo

Hi, In sc_main function I have a sc_clock and I instance a module A, too. Now inside module A, I want to get period of that sc_clock to delay. Thanks, VanTeo

Thanks er_sud

Hi, I have a module. My module has two port: sc_in_clk SCKi sc_in<sc_bv<12>> RXDi and has a process: SC_THREAD(do_thread) sensitive << RXDi; In sc_main I will do: RXDi.write("111111111111"); Now I want to implement do_thread to data on RXDi will delay in 16-cycles of SCKi. Please help me, thanks, VanTeo

Oh thanks Cliffe Fei, I have understand

Sorry Philipp, because I'm a beginer so I understand your mind clearly. When I remove SCI_func("sci_func"), it's error error C2512: 'SCI_func' : no appropriate default constructor available Thanks, VanTeo

Hi all, I have a problem with my project Error: (E100) port specified outside of module: port 'RXDi' (sc_port_base) In file: ..\..\src\sysc\communication\sc_port.cpp:231 this is my codes #include "SCI.h" #include "conio.h" int sc_main(int argc,char* argv[]) { SCI SCI_01("SCI_01"); sc_signal<sc_bv<8>> RXDi; SCI_01.RXDi(RXDi); SCI_01.SCI_setting("asynchronous", "external_clock", "7-bit", "parity", "even", "two_stopbit", "1/1", "MSB"); SCI_01.SCI_BitRate(32); //RXDi.write("00000000"); sc_start(); //sc_stop(); getch(); return 0; } #include "SCI_function.h" class SCI: public SCI_func { public: sc_in<sc_bv<8>> RXDi; //sc_out<sc_bv<8>> TXDi; //sc_inout<sc_bv<1>> SCKi; sc_event recei_done; //sc_bv<8> recei_temp; public: SC_CTOR(SCI): RXDi("RXDi"), SCI_func("sci_func") { cout << "in constructor of " << name() << endl; //SCI_setting("asynchronous", "external_clock", "7-bit", "parity", "even", "two_stopbit", "1/1", "MSB"); //SCI_BitRate(32); //SCI_WBuffTrans("11111111"); //SCI_setting("synchronous", "external_clock", "1/4", "LSB", "polarity", "delay_clock"); SC_THREAD(SCI_trans_synchronous); //sensitive << recei_data; SC_METHOD(SCI_recei_synchronous); sensitive << RXDi; } void SCI_trans_synchronous(); void SCI_recei_synchronous(); }; void SCI::SCI_trans_synchronous() { wait(recei_done); cout << "OK!!!!"; } void SCI::SCI_recei_synchronous() { //processing data receive if(reg_SCiSR->read_bit<1>("TBEF") == 1) { reg_SCiTB->write(RXDi.read()); } recei_done.notify(); } the SCI_func class inherit from SCI_reg class, SCI_reg class inherit from sc_module class thanks all, VanTeo

thanks Alan

Hi all, I am a novice in systemC. When I learn about systemC from examples, I find that SC_MODULE will be used for combination logic and SC_THREAD will be used for sequential logic. Why is it? Can you explain to me clearly, please? How do SC_MODULE and SC_THREAD work? Thank you,

thank Alan

Hi all, I have a problem with my assignment. I have "General_Register" class, this class has constructor which will receive arguments: General_Reg(sc_module_name reg_Name_, sc_uint<N> reg_DataDefault_, int reg_BitRangeNum_, string bit_Name_[], int bit_Start_[], int bit_Length_[], int bit_Status_[]): sc_module(reg_Name_), reg_Name(reg_Name_), reg_DataDefault(reg_DataDefault_), reg_BitRangeNum(reg_BitRangeNum_), bit_Name(bit_Name_), bit_Start(bit_Start_), bit_Length(bit_Length_), bit_Status(bit_Status_) I have "Generator_Register" class, too. This class has constructor which will receive arguments: Generator_Register(sc_module_name reg_Name_, string file_name_): sc_module(reg_Name_), reg_Name(reg_Name_), file_name(file_name_) and instance the object of "General_Register" class: General_Reg<N> reg_Name(reg_Name, reg_Default, bit_RangeNum, bit_Name, bit_Start, bit_Length, bit_Status); when I run it, it have error: Error: (E513) an sc_module_name parameter for your constructor is required In file: ..\..\src\sysc\kernel\sc_module.cpp:220 Help me, please! My codes were attach below general_register.txt generator_register.txt

Hi Alan, I have declared int d; i want to show the result of tranfering transaction from initiator to target through "d" variable. Kartik Gurlhosur helped me add sc_out<int> dummy_port within Memory and connect memory[0]->dummy_port(d[0]) (Similar to memory[1,2,3]), it ran ok

Hi Kartik Gurlhosur thanks your replay but it's not right c:\users\giahuy\onedrive\tlm\example\routing - copy - copy\routing\routing\main.cpp(44): error C2676: binary '[' : 'sc_core::sc_signal<T>' does not define this operator or a conversion to a type acceptable to the predefined operator 1> with 1> [ 1> T=int 1> ] 1>c:\users\giahuy\onedrive\tlm\example\routing - copy - copy\routing\routing\main.cpp(44): error C2064: term does not evaluate to a function taking 1 arguments 1> 1>Build FAILED. 1> 1>Time Elapsed 00:00:06.73 ========== Build: 0 succeeded, 1 failed, 0 up-to-date, 0 skipped ========== help me please