shreyasraju
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Posts posted by shreyasraju
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Hi uwes,
The issue is, I call field.mirror(UVM_CHECK). This should ideally read the field and check only that field with the mirror register field. However, the field.mirror() task is now comparing the entire register with the mirror which I don't want to do. Can you give me a solution to overcome this?
Shreyas
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Hi,
I wanted to use the field.mirror() task provided in the uvm_reg_field class to check only a particular field. However, I see that the field.mirror() task is just calling the parent register mirror task. Hence the entire register is read and compared which I didn't intend to do. I tried this in my sequence and I see the above mentioned behavior. This looks like a serious bug. Can you please confirm this.
Regards,
Shreyas
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Hi all,
What exactly is the difference between uvm_hdl_force and uvm_hdl_deposit? The UVM Class reference document doesn't provide much explanation. Please help.
Thanks,
Shreyas
field.mirror() task not working as expected
in UVM SystemVerilog Discussions
Posted
Hi David,
I'm not comparing the desired value. I'm comparing the read back value with the mirror value. The read back and compare is done in the mirror task which is convenient to use. Otherwise I will have to read the register and compare only the field bits, which will require some code to be written.
Regards,
Shreyas