Jump to content

UVM / OVM Harness Whitepaper 1.2

About This File

This update adds a section that addresses how to connect harnesses to arrays of sub-modules in a virtual harness.

Harnesses are a proven methodology to hierarchically reuse interface connections from the block to the chip level.

Included in the package are instructions for both UVM and OVM test benches.

User Feedback

Recommended Comments

There are no comments to display.

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Add a comment...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Create New...